disturb.tan.qmsg

适用于初学者的一个m序列扰、解码器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register Dif:D7\|tp Dif:D5\|tp 422.12 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 422.12 MHz between source register \"Dif:D7\|tp\" and destination register \"Dif:D5\|tp\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.825 ns + Longest register register " "Info: + Longest register to register delay is 0.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Dif:D7\|tp 1 REG LC_X52_Y10_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Dif:D7|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.075 ns) 0.468 ns inst~13 2 COMB LC_X52_Y10_N6 2 " "Info: 2: + IC(0.393 ns) + CELL(0.075 ns) = 0.468 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { Dif:D7|tp inst~13 } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 104 168 232 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 0.825 ns Dif:D5\|tp 3 REG LC_X52_Y10_N7 1 " "Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 0.825 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.357 ns" { inst~13 Dif:D5|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.298 ns ( 36.12 % ) " "Info: Total cell delay = 0.298 ns ( 36.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.527 ns ( 63.88 % ) " "Info: Total interconnect delay = 0.527 ns ( 63.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.825 ns" { Dif:D7|tp inst~13 Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.825 ns" { Dif:D7|tp inst~13 Dif:D5|tp } { 0.000ns 0.393ns 0.134ns } { 0.000ns 0.075ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.986 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 232 -8 160 248 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns Dif:D5\|tp 2 REG LC_X52_Y10_N7 1 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.158 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.986 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 232 -8 160 248 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns Dif:D7\|tp 2 REG LC_X52_Y10_N9 2 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.158 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D7|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D7|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.825 ns" { Dif:D7|tp inst~13 Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.825 ns" { Dif:D7|tp inst~13 Dif:D5|tp } { 0.000ns 0.393ns 0.134ns } { 0.000ns 0.075ns 0.223ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D7|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { Dif:D5|tp } {  } {  } "" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Dif:D5\|tp input CLK 2.058 ns register " "Info: tsu for register \"Dif:D5\|tp\" (data pin = \"input\", clock pin = \"CLK\") is 2.058 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.034 ns + Longest pin register " "Info: + Longest pin to register delay is 5.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns input 1 PIN PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_P2; Fanout = 2; PIN Node = 'input'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { input } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 128 -8 160 144 "input" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.163 ns) + CELL(0.280 ns) 4.677 ns inst~13 2 COMB LC_X52_Y10_N6 2 " "Info: 2: + IC(3.163 ns) + CELL(0.280 ns) = 4.677 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.443 ns" { input inst~13 } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 104 168 232 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 5.034 ns Dif:D5\|tp 3 REG LC_X52_Y10_N7 1 " "Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 5.034 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.357 ns" { inst~13 Dif:D5|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns ( 34.51 % ) " "Info: Total cell delay = 1.737 ns ( 34.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.297 ns ( 65.49 % ) " "Info: Total interconnect delay = 3.297 ns ( 65.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.034 ns" { input inst~13 Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.034 ns" { input input~out0 inst~13 Dif:D5|tp } { 0.000ns 0.000ns 3.163ns 0.134ns } { 0.000ns 1.234ns 0.280ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.986 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 232 -8 160 248 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns Dif:D5\|tp 2 REG LC_X52_Y10_N7 1 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.158 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.034 ns" { input inst~13 Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.034 ns" { input input~out0 inst~13 Dif:D5|tp } { 0.000ns 0.000ns 3.163ns 0.134ns } { 0.000ns 1.234ns 0.280ns 0.223ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK disturb Dif:D7\|tp 6.907 ns register " "Info: tco from clock \"CLK\" to destination pin \"disturb\" through register \"Dif:D7\|tp\" is 6.907 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.986 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 232 -8 160 248 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns Dif:D7\|tp 2 REG LC_X52_Y10_N9 2 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.158 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D7|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.765 ns + Longest register pin " "Info: + Longest register to pin delay is 3.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Dif:D7\|tp 1 REG LC_X52_Y10_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Dif:D7|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.075 ns) 0.468 ns inst~13 2 COMB LC_X52_Y10_N6 2 " "Info: 2: + IC(0.393 ns) + CELL(0.075 ns) = 0.468 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { Dif:D7|tp inst~13 } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 104 168 232 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(2.376 ns) 3.765 ns disturb 3 PIN PIN_P3 0 " "Info: 3: + IC(0.921 ns) + CELL(2.376 ns) = 3.765 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'disturb'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.297 ns" { inst~13 disturb } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 248 696 872 264 "disturb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.451 ns ( 65.10 % ) " "Info: Total cell delay = 2.451 ns ( 65.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.314 ns ( 34.90 % ) " "Info: Total interconnect delay = 1.314 ns ( 34.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.765 ns" { Dif:D7|tp inst~13 disturb } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.765 ns" { Dif:D7|tp inst~13 disturb } { 0.000ns 0.393ns 0.921ns } { 0.000ns 0.075ns 2.376ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D7|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D7|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.765 ns" { Dif:D7|tp inst~13 disturb } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.765 ns" { Dif:D7|tp inst~13 disturb } { 0.000ns 0.393ns 0.921ns } { 0.000ns 0.075ns 2.376ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "input disturb 7.974 ns Longest " "Info: Longest tpd from source pin \"input\" to destination pin \"disturb\" is 7.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns input 1 PIN PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_P2; Fanout = 2; PIN Node = 'input'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { input } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 128 -8 160 144 "input" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.163 ns) + CELL(0.280 ns) 4.677 ns inst~13 2 COMB LC_X52_Y10_N6 2 " "Info: 2: + IC(3.163 ns) + CELL(0.280 ns) = 4.677 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.443 ns" { input inst~13 } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 104 168 232 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(2.376 ns) 7.974 ns disturb 3 PIN PIN_P3 0 " "Info: 3: + IC(0.921 ns) + CELL(2.376 ns) = 7.974 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'disturb'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.297 ns" { inst~13 disturb } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 248 696 872 264 "disturb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.890 ns ( 48.78 % ) " "Info: Total cell delay = 3.890 ns ( 48.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.084 ns ( 51.22 % ) " "Info: Total interconnect delay = 4.084 ns ( 51.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.974 ns" { input inst~13 disturb } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.974 ns" { input input~out0 inst~13 disturb } { 0.000ns 0.000ns 3.163ns 0.921ns } { 0.000ns 1.234ns 0.280ns 2.376ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}