disturb.map.rpt

适用于初学者的一个m序列扰、解码器

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                  ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                  ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
; Dif.vhd                          ; yes             ; User VHDL File                     ; C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd     ;
; Disturb.bdf                      ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 6     ;
;     -- Combinational with no register       ; 1     ;
;     -- Register only                        ; 5     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 1     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 6     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 5     ;
; I/O pins                                    ; 4     ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 5     ;
; Total fan-out                               ; 15    ;
; Average fan-out                             ; 1.50  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |Disturb                   ; 6 (1)       ; 5            ; 0           ; 0            ; 0       ; 0         ; 0         ; 4    ; 0            ; 1 (1)        ; 5 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Disturb            ;              ;
;    |Dif:D5|                ; 1 (1)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Disturb|Dif:D5     ; work         ;
;    |Dif:D6|                ; 1 (1)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Disturb|Dif:D6     ; work         ;
;    |Dif:D7|                ; 1 (1)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Disturb|Dif:D7     ; work         ;
;    |Dif:D8|                ; 1 (1)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Disturb|Dif:D8     ; work         ;
;    |Dif:D9|                ; 1 (1)       ; 1            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Disturb|Dif:D9     ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; D0/tp                                 ; Merged with D5/tp  ;
; D1/tp                                 ; Merged with D6/tp  ;
; D2/tp                                 ; Merged with D7/tp  ;
; D3/tp                                 ; Merged with D8/tp  ;
; D4/tp                                 ; Merged with D9/tp  ;
; Total Number of Removed Registers = 5 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Dec 17 19:52:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Disturb -c Disturb
Info: Found 2 design units, including 1 entities, in source file Dif.vhd
    Info: Found design unit 1: Dif-behave
    Info: Found entity 1: Dif
Info: Found 1 design units, including 1 entities, in source file Disturb.bdf
    Info: Found entity 1: Disturb
Info: Elaborating entity "Disturb" for the top level hierarchy
Info: Elaborating entity "Dif" for hierarchy "Dif:D4"
Warning (10492): VHDL Process Statement warning at Dif.vhd(16): signal "tp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "Dif:D0|tp" merged to single register "Dif:D5|tp"
    Info: Duplicate register "Dif:D1|tp" merged to single register "Dif:D6|tp"
    Info: Duplicate register "Dif:D2|tp" merged to single register "Dif:D7|tp"
    Info: Duplicate register "Dif:D3|tp" merged to single register "Dif:D8|tp"
    Info: Duplicate register "Dif:D4|tp" merged to single register "Dif:D9|tp"
Info: Implemented 10 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 2 output pins
    Info: Implemented 6 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 150 megabytes of memory during processing
    Info: Processing ended: Wed Dec 17 19:52:34 2008
    Info: Elapsed time: 00:00:03