disturb.tan.rpt

适用于初学者的一个m序列扰、解码器

; tco                                                                  ;
+-------+--------------+------------+-----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To      ; From Clock ;
+-------+--------------+------------+-----------+---------+------------+
; N/A   ; None         ; 6.907 ns   ; Dif:D7|tp ; disturb ; CLK        ;
; N/A   ; None         ; 6.669 ns   ; Dif:D9|tp ; disturb ; CLK        ;
+-------+--------------+------------+-----------+---------+------------+


+---------------------------------------------------------------+
; tpd                                                           ;
+-------+-------------------+-----------------+-------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To      ;
+-------+-------------------+-----------------+-------+---------+
; N/A   ; None              ; 7.974 ns        ; input ; disturb ;
; N/A   ; None              ; 7.245 ns        ; input ; output  ;
+-------+-------------------+-----------------+-------+---------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; -1.948 ns ; input ; Dif:D5|tp ; CLK      ;
+---------------+-------------+-----------+-------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Dec 17 19:52:54 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Disturb -c Disturb --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 422.12 MHz between source register "Dif:D7|tp" and destination register "Dif:D5|tp"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.825 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7|tp'
            Info: 2: + IC(0.393 ns) + CELL(0.075 ns) = 0.468 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'
            Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 0.825 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5|tp'
            Info: Total cell delay = 0.298 ns ( 36.12 % )
            Info: Total interconnect delay = 0.527 ns ( 63.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.986 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5|tp'
                Info: Total cell delay = 1.370 ns ( 45.88 % )
                Info: Total interconnect delay = 1.616 ns ( 54.12 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.986 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7|tp'
                Info: Total cell delay = 1.370 ns ( 45.88 % )
                Info: Total interconnect delay = 1.616 ns ( 54.12 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "Dif:D5|tp" (data pin = "input", clock pin = "CLK") is 2.058 ns
    Info: + Longest pin to register delay is 5.034 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_P2; Fanout = 2; PIN Node = 'input'
        Info: 2: + IC(3.163 ns) + CELL(0.280 ns) = 4.677 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'
        Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 5.034 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5|tp'
        Info: Total cell delay = 1.737 ns ( 34.51 % )
        Info: Total interconnect delay = 3.297 ns ( 65.49 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.986 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5|tp'
        Info: Total cell delay = 1.370 ns ( 45.88 % )
        Info: Total interconnect delay = 1.616 ns ( 54.12 % )
Info: tco from clock "CLK" to destination pin "disturb" through register "Dif:D7|tp" is 6.907 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.986 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7|tp'
        Info: Total cell delay = 1.370 ns ( 45.88 % )
        Info: Total interconnect delay = 1.616 ns ( 54.12 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.765 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y10_N9; Fanout = 2; REG Node = 'Dif:D7|tp'
        Info: 2: + IC(0.393 ns) + CELL(0.075 ns) = 0.468 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'
        Info: 3: + IC(0.921 ns) + CELL(2.376 ns) = 3.765 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'disturb'
        Info: Total cell delay = 2.451 ns ( 65.10 % )
        Info: Total interconnect delay = 1.314 ns ( 34.90 % )
Info: Longest tpd from source pin "input" to destination pin "disturb" is 7.974 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_P2; Fanout = 2; PIN Node = 'input'
    Info: 2: + IC(3.163 ns) + CELL(0.280 ns) = 4.677 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'
    Info: 3: + IC(0.921 ns) + CELL(2.376 ns) = 7.974 ns; Loc. = PIN_P3; Fanout = 0; PIN Node = 'disturb'
    Info: Total cell delay = 3.890 ns ( 48.78 % )
    Info: Total interconnect delay = 4.084 ns ( 51.22 % )
Info: th for register "Dif:D5|tp" (data pin = "input", clock pin = "CLK") is -1.948 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.986 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5|tp'
        Info: Total cell delay = 1.370 ns ( 45.88 % )
        Info: Total interconnect delay = 1.616 ns ( 54.12 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.034 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_P2; Fanout = 2; PIN Node = 'input'
        Info: 2: + IC(3.163 ns) + CELL(0.280 ns) = 4.677 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'
        Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 5.034 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5|tp'
        Info: Total cell delay = 1.737 ns ( 34.51 % )
        Info: Total interconnect delay = 3.297 ns ( 65.49 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Wed Dec 17 19:52:55 2008
    Info: Elapsed time: 00:00:01