dif.vhd.bak

适用于初学者的一个m序列扰、解码器

Library ieee;
use ieee.std_logic_1164.all;
entity Dif is
port( D,clk:in std_logic;
      Q:out std_logic
     );
end Dif;
architecture behave of Dif is
   signal tp: std_logic;
   begin
   process(clk)
   begin
   if clk'event and clk='1' then
      tp<=D;
   end if;
   Q<=tp;
   end process;
end behave;