📄 uart_top.sim.qmsg

📁 实现FPGA和上位机的串口通信
💻 QMSG
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 30 15:31:35 2008 " "Info: Processing started: Tue Dec 30 15:31:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off uart_top -c uart_top " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off uart_top -c uart_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf " "Info: Using vector source file \"C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ce " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ce\" in design." {  } { { "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf" "" { Waveform "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf" "ce" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "bg_out " "Warning: Ignored node in vector source file. Can't find corresponding node name \"bg_out\" in design." {  } { { "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf" "" { Waveform "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf" "bg_out" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "indicator " "Warning: Ignored node in vector source file. Can't find corresponding node name \"indicator\" in design." {  } { { "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf" "" { Waveform "C:/altera/70/qdesigns/PROGRAM/UART_SUCCESS/baudrate_generator.vwf" "indicator" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|RxD " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|RxD\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[5\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[5\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[4\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[4\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[3\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[3\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[6\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[6\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[0\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[0\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[7\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[7\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[2\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[2\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|uart_top\|send_bus\[1\] " "Warning: Can't find signal in vector source file for input pin \"\|uart_top\|send_bus\[1\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|dout " "Info: Register: \|uart_top\|shift_register:U_SR\|dout" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[0\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[1\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[2\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[3\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[4\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[5\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[6\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[7\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[8\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|shift_register:U_SR\|shift_regs\[9\] " "Info: Register: \|uart_top\|shift_register:U_SR\|shift_regs\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|counter:U_Counter\|count\[31\] " "Info: Register: \|uart_top\|counter:U_Counter\|count\[31\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|counter:U_Counter\|count\[0\] " "Info: Register: \|uart_top\|counter:U_Counter\|count\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[15\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[15\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[7\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[8\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[13\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[13\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[14\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[14\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[12\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[12\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[2\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[4\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[6\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[10\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[10\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[0\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[1\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[3\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[5\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[9\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[11\] " "Info: Register: \|uart_top\|baudrate_generator:U_BG\|\\main:clk_count\[11\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|uart_core:U_Core\|reset_dt " "Info: Register: \|uart_top\|uart_core:U_Core\|reset_dt" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_top\|sld_hub:sld_hub_inst\|hub_tdo~reg0 " "Info: Register: \|uart_top\|sld_hub:sld_hub_inst\|hub_tdo~reg0" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations accordin
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