uart_top.map.qmsg

实现FPGA和上位机的串口通信

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART_PACKAGE.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file UART_PACKAGE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_PACKAGE " "Info: Found design unit 1: UART_PACKAGE" {  } { { "UART_PACKAGE.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/UART_PACKAGE.vhd" 6 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_PACKAGE-body " "Info: Found design unit 2: UART_PACKAGE-body" {  } { { "UART_PACKAGE.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/UART_PACKAGE.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_top-uart_top " "Info: Found design unit 1: uart_top-uart_top" {  } { { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 42 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_top " "Info: Found entity 1: uart_top" {  } { { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_top " "Info: Elaborating entity \"uart_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baudrate_generator baudrate_generator:U_BG " "Info: Elaborating entity \"baudrate_generator\" for hierarchy \"baudrate_generator:U_BG\"" {  } { { "uart_top.vhd" "U_BG" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 191 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switch_bus switch_bus:U_BusSwitch " "Info: Elaborating entity \"switch_bus\" for hierarchy \"switch_bus:U_BusSwitch\"" {  } { { "uart_top.vhd" "U_BusSwitch" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 200 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_core uart_core:U_Core " "Info: Elaborating entity \"uart_core\" for hierarchy \"uart_core:U_Core\"" {  } { { "uart_top.vhd" "U_Core" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 208 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:U_Counter " "Info: Elaborating entity \"counter\" for hierarchy \"counter:U_Counter\"" {  } { { "uart_top.vhd" "U_Counter" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 232 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "switch switch:U_CounterClkSwitch " "Info: Elaborating entity \"switch\" for hierarchy \"switch:U_CounterClkSwitch\"" {  } { { "uart_top.vhd" "U_CounterClkSwitch" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 240 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector detector:U_Detector " "Info: Elaborating entity \"detector\" for hierarchy \"detector:U_Detector\"" {  } { { "uart_top.vhd" "U_Detector" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 248 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "parity_verifier parity_verifier:U_ParityVerifier " "Info: Elaborating entity \"parity_verifier\" for hierarchy \"parity_verifier:U_ParityVerifier\"" {  } { { "uart_top.vhd" "U_ParityVerifier" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 256 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_register shift_register:U_SR " "Info: Elaborating entity \"shift_register\" for hierarchy \"shift_register:U_SR\"" {  } { { "uart_top.vhd" "U_SR" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 270 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}