uart_top.map.qmsg

实现FPGA和上位机的串口通信

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 29 15:50:11 2008 " "Info: Processing started: Mon Dec 29 15:50:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_top -c uart_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_top -c uart_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baudrate_generator.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file baudrate_generator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baudrate_generator-baudrate_generator " "Info: Found design unit 1: baudrate_generator-baudrate_generator" {  } { { "baudrate_generator.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/baudrate_generator.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 baudrate_generator " "Info: Found entity 1: baudrate_generator" {  } { { "baudrate_generator.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/baudrate_generator.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter " "Info: Found design unit 1: counter-counter" {  } { { "counter.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/counter.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/counter.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "detector.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file detector.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 detector-detector " "Info: Found design unit 1: detector-detector" {  } { { "detector.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/detector.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 detector " "Info: Found entity 1: detector" {  } { { "detector.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/detector.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parity_verifier.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file parity_verifier.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 parity_verifier-parity_verifier " "Info: Found design unit 1: parity_verifier-parity_verifier" {  } { { "parity_verifier.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/parity_verifier.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 parity_verifier " "Info: Found entity 1: parity_verifier" {  } { { "parity_verifier.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/parity_verifier.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift_register.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shift_register.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_register-shift_register " "Info: Found design unit 1: shift_register-shift_register" {  } { { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 shift_register " "Info: Found entity 1: shift_register" {  } { { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file switch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 switch-switch " "Info: Found design unit 1: switch-switch" {  } { { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 switch " "Info: Found entity 1: switch" {  } { { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "switch_bus.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file switch_bus.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 switch_bus-switch_bus " "Info: Found design unit 1: switch_bus-switch_bus" {  } { { "switch_bus.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch_bus.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 switch_bus " "Info: Found entity 1: switch_bus" {  } { { "switch_bus.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch_bus.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_core.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart_core.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_core-uart_core " "Info: Found design unit 1: uart_core-uart_core" {  } { { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_core " "Info: Found entity 1: uart_core" {  } { { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}