uart_top.hier_info

实现FPGA和上位机的串口通信

|uart_top
clk => detector:U_Detector.clk
clk => uart_core:U_Core.clk
clk => baudrate_generator:U_BG.clk
clk => switch:U_SRClkSwitch.din2
clk => switch:U_CounterClkSwitch.din2
reset_n => uart_core:U_Core.reset_n
send => uart_core:U_Core.send
send_bus[0] => uart_core:U_Core.send_bus[0]
send_bus[0] => switch_bus:U_BusSwitch.din1[0]
send_bus[1] => uart_core:U_Core.send_bus[1]
send_bus[1] => switch_bus:U_BusSwitch.din1[1]
send_bus[2] => uart_core:U_Core.send_bus[2]
send_bus[2] => switch_bus:U_BusSwitch.din1[2]
send_bus[3] => uart_core:U_Core.send_bus[3]
send_bus[3] => switch_bus:U_BusSwitch.din1[3]
send_bus[4] => uart_core:U_Core.send_bus[4]
send_bus[4] => switch_bus:U_BusSwitch.din1[4]
send_bus[5] => uart_core:U_Core.send_bus[5]
send_bus[5] => switch_bus:U_BusSwitch.din1[5]
send_bus[6] => uart_core:U_Core.send_bus[6]
send_bus[6] => switch_bus:U_BusSwitch.din1[6]
send_bus[7] => uart_core:U_Core.send_bus[7]
send_bus[7] => switch_bus:U_BusSwitch.din1[7]
send_over <= uart_core:U_Core.send_over
error <= uart_core:U_Core.error
recv <= uart_core:U_Core.recv
recv_bus[0] <= uart_core:U_Core.recv_bus[0]
recv_bus[1] <= uart_core:U_Core.recv_bus[1]
recv_bus[2] <= uart_core:U_Core.recv_bus[2]
recv_bus[3] <= uart_core:U_Core.recv_bus[3]
recv_bus[4] <= uart_core:U_Core.recv_bus[4]
recv_bus[5] <= uart_core:U_Core.recv_bus[5]
recv_bus[6] <= uart_core:U_Core.recv_bus[6]
recv_bus[7] <= uart_core:U_Core.recv_bus[7]
RxD => switch:U_SISwitch.din2
RxD => detector:U_Detector.RxD
TxD <= switch:U_TXDSwitch.dout


|uart_top|baudrate_generator:U_BG
clk => indicator~reg0.CLK
clk => bg_out~reg0.CLK
clk => \main:clk_count[0].CLK
clk => \main:clk_count[1].CLK
clk => \main:clk_count[2].CLK
clk => \main:clk_count[3].CLK
clk => \main:clk_count[4].CLK
clk => \main:clk_count[5].CLK
clk => \main:clk_count[6].CLK
clk => \main:clk_count[7].CLK
clk => \main:clk_count[8].CLK
clk => \main:clk_count[9].CLK
clk => \main:clk_count[10].CLK
clk => \main:clk_count[11].CLK
clk => \main:clk_count[12].CLK
clk => \main:clk_count[13].CLK
clk => \main:clk_count[14].CLK
clk => \main:clk_count[15].CLK
reset_n => indicator~reg0.ACLR
reset_n => bg_out~reg0.ACLR
reset_n => \main:clk_count[0].ACLR
reset_n => \main:clk_count[1].ACLR
reset_n => \main:clk_count[2].ACLR
reset_n => \main:clk_count[3].ACLR
reset_n => \main:clk_count[4].ACLR
reset_n => \main:clk_count[5].ACLR
reset_n => \main:clk_count[6].ACLR
reset_n => \main:clk_count[7].ACLR
reset_n => \main:clk_count[8].ACLR
reset_n => \main:clk_count[9].ACLR
reset_n => \main:clk_count[10].ACLR
reset_n => \main:clk_count[11].ACLR
reset_n => \main:clk_count[12].ACLR
reset_n => \main:clk_count[13].ACLR
reset_n => \main:clk_count[14].ACLR
reset_n => \main:clk_count[15].ACLR
ce => indicator~reg0.ENA
ce => bg_out~reg0.ENA
ce => \main:clk_count[0].ENA
ce => \main:clk_count[1].ENA
ce => \main:clk_count[2].ENA
ce => \main:clk_count[3].ENA
ce => \main:clk_count[4].ENA
ce => \main:clk_count[5].ENA
ce => \main:clk_count[6].ENA
ce => \main:clk_count[7].ENA
ce => \main:clk_count[8].ENA
ce => \main:clk_count[9].ENA
ce => \main:clk_count[10].ENA
ce => \main:clk_count[11].ENA
ce => \main:clk_count[12].ENA
ce => \main:clk_count[13].ENA
ce => \main:clk_count[14].ENA
ce => \main:clk_count[15].ENA
bg_out <= bg_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
indicator <= indicator~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|switch_bus:U_BusSwitch
din1[0] => dout~7.DATAB
din1[1] => dout~6.DATAB
din1[2] => dout~5.DATAB
din1[3] => dout~4.DATAB
din1[4] => dout~3.DATAB
din1[5] => dout~2.DATAB
din1[6] => dout~1.DATAB
din1[7] => dout~0.DATAB
din2[0] => dout~7.DATAA
din2[1] => dout~6.DATAA
din2[2] => dout~5.DATAA
din2[3] => dout~4.DATAA
din2[4] => dout~3.DATAA
din2[5] => dout~2.DATAA
din2[6] => dout~1.DATAA
din2[7] => dout~0.DATAA
sel => dout~0.OUTPUTSELECT
sel => dout~1.OUTPUTSELECT
sel => dout~2.OUTPUTSELECT
sel => dout~3.OUTPUTSELECT
sel => dout~4.OUTPUTSELECT
sel => dout~5.OUTPUTSELECT
sel => dout~6.OUTPUTSELECT
sel => dout~7.OUTPUTSELECT
dout[0] <= dout~7.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout~6.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout~5.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout~4.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout~3.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout~1.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|uart_core:U_Core
clk => si_count[0].CLK
clk => si_count[1].CLK
clk => si_count[2].CLK
clk => si_count[3].CLK
clk => recv_bus[0]~reg0.CLK
clk => recv_bus[1]~reg0.CLK
clk => recv_bus[2]~reg0.CLK
clk => recv_bus[3]~reg0.CLK
clk => recv_bus[4]~reg0.CLK
clk => recv_bus[5]~reg0.CLK
clk => recv_bus[6]~reg0.CLK
clk => recv_bus[7]~reg0.CLK
clk => error~reg0.CLK
clk => recv~reg0.CLK
clk => send_over~reg0.CLK
clk => sel_out~reg0.CLK
clk => sel_pv~reg0.CLK
clk => sel_clk~reg0.CLK
clk => sel_si~reg0.CLK
clk => ce_parts~reg0.CLK
clk => reset_parts~reg0.CLK
clk => reset_dt~reg0.CLK
clk => state~21.IN1
reset_n => si_count[0].ACLR
reset_n => si_count[1].ACLR
reset_n => si_count[2].ACLR
reset_n => si_count[3].ACLR
reset_n => recv_bus[0]~reg0.ACLR
reset_n => recv_bus[1]~reg0.ACLR
reset_n => recv_bus[2]~reg0.ACLR
reset_n => recv_bus[3]~reg0.ACLR
reset_n => recv_bus[4]~reg0.ACLR
reset_n => recv_bus[5]~reg0.ACLR
reset_n => recv_bus[6]~reg0.ACLR
reset_n => recv_bus[7]~reg0.ACLR
reset_n => error~reg0.ACLR
reset_n => recv~reg0.ACLR
reset_n => send_over~reg0.ACLR
reset_n => sel_out~reg0.ACLR
reset_n => sel_pv~reg0.ACLR
reset_n => sel_clk~reg0.ACLR
reset_n => sel_si~reg0.ACLR
reset_n => ce_parts~reg0.ACLR
reset_n => reset_parts~reg0.ACLR
reset_n => reset_dt~reg0.PRESET
reset_n => send_si~0.OUTPUTSELECT
reset_n => state~22.IN1
new_data => reset_parts~1.OUTPUTSELECT
new_data => ce_parts~1.OUTPUTSELECT
new_data => sel_si~1.OUTPUTSELECT
new_data => sel_clk~1.OUTPUTSELECT
new_data => sel_out~1.OUTPUTSELECT
new_data => sel_pv~1.OUTPUTSELECT
new_data => state~6.OUTPUTSELECT
new_data => state~7.OUTPUTSELECT
new_data => state~8.OUTPUTSELECT
new_data => state~9.OUTPUTSELECT
new_data => state~10.OUTPUTSELECT
new_data => state~11.OUTPUTSELECT
new_data => si_count~4.OUTPUTSELECT
new_data => si_count~5.OUTPUTSELECT
new_data => si_count~6.OUTPUTSELECT
new_data => si_count~7.OUTPUTSELECT
new_data => reset_dt~1.OUTPUTSELECT
reset_dt <= reset_dt~reg0.DB_MAX_OUTPUT_PORT_TYPE
reset_parts <= reset_parts~reg0.DB_MAX_OUTPUT_PORT_TYPE
ce_parts <= ce_parts~reg0.DB_MAX_OUTPUT_PORT_TYPE
send_si <= send_si~0.DB_MAX_OUTPUT_PORT_TYPE
sel_si <= sel_si~reg0.DB_MAX_OUTPUT_PORT_TYPE
regs[0] => main~0.IN0
regs[1] => recv_bus~7.DATAB
regs[2] => recv_bus~6.DATAB
regs[3] => recv_bus~5.DATAB
regs[4] => recv_bus~4.DATAB
regs[5] => recv_bus~3.DATAB
regs[6] => recv_bus~2.DATAB
regs[7] => recv_bus~1.DATAB
regs[8] => recv_bus~0.DATAB
regs[9] => ~NO_FANOUT~
sel_clk <= sel_clk~reg0.DB_MAX_OUTPUT_PORT_TYPE
overflow => sel_si~2.OUTPUTSELECT
overflow => sel_out~2.OUTPUTSELECT
overflow => sel_pv~2.OUTPUTSELECT
overflow => state~12.OUTPUTSELECT
overflow => state~13.OUTPUTSELECT
overflow => state~14.OUTPUTSELECT
overflow => state~15.OUTPUTSELECT
overflow => state~16.OUTPUTSELECT
overflow => state~17.OUTPUTSELECT
overflow => si_count~12.OUTPUTSELECT
overflow => si_count~13.OUTPUTSELECT
overflow => si_count~14.OUTPUTSELECT
overflow => si_count~15.OUTPUTSELECT
overflow => send_over~0.OUTPUTSELECT
overflow => state~18.OUTPUTSELECT
overflow => state~19.OUTPUTSELECT
overflow => reset_parts~2.OUTPUTSELECT
overflow => ce_parts~2.OUTPUTSELECT
overflow => recv~0.OUTPUTSELECT
overflow => recv_bus~0.OUTPUTSELECT
overflow => recv_bus~1.OUTPUTSELECT
overflow => recv_bus~2.OUTPUTSELECT
overflow => recv_bus~3.OUTPUTSELECT
overflow => recv_bus~4.OUTPUTSELECT
overflow => recv_bus~5.OUTPUTSELECT
overflow => recv_bus~6.OUTPUTSELECT
overflow => recv_bus~7.OUTPUTSELECT
overflow => state~20.OUTPUTSELECT
overflow => Selector0.IN1
overflow => Selector1.IN2
overflow => Selector3.IN1
sel_pv <= sel_pv~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity => main~0.IN1
sel_out <= sel_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
send => reset_parts~0.OUTPUTSELECT
send => ce_parts~0.OUTPUTSELECT
send => sel_si~0.OUTPUTSELECT
send => sel_clk~0.OUTPUTSELECT
send => sel_out~0.OUTPUTSELECT
send => sel_pv~0.OUTPUTSELECT
send => state~0.OUTPUTSELECT
send => state~1.OUTPUTSELECT
send => state~2.OUTPUTSELECT
send => state~3.OUTPUTSELECT
send => state~4.OUTPUTSELECT
send => state~5.OUTPUTSELECT
send => si_count~0.OUTPUTSELECT
send => si_count~1.OUTPUTSELECT
send => si_count~2.OUTPUTSELECT
send => si_count~3.OUTPUTSELECT
send => reset_dt~0.OUTPUTSELECT
send_bus[0] => Mux0.IN15
send_bus[1] => Mux0.IN14
send_bus[2] => Mux0.IN13
send_bus[3] => Mux0.IN12
send_bus[4] => Mux0.IN11
send_bus[5] => Mux0.IN10
send_bus[6] => Mux0.IN9
send_bus[7] => Mux0.IN8
send_over <= send_over~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv <= recv~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[0] <= recv_bus[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[1] <= recv_bus[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[2] <= recv_bus[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[3] <= recv_bus[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[4] <= recv_bus[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[5] <= recv_bus[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[6] <= recv_bus[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
recv_bus[7] <= recv_bus[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
error <= error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|counter:U_Counter
clk => overflow~reg0.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => count[7].CLK
clk => count[8].CLK
clk => count[9].CLK
clk => count[10].CLK
clk => count[11].CLK
clk => count[12].CLK
clk => count[13].CLK
clk => count[14].CLK
clk => count[15].CLK
clk => count[16].CLK
clk => count[17].CLK
clk => count[18].CLK
clk => count[19].CLK
clk => count[20].CLK
clk => count[21].CLK
clk => count[22].CLK
clk => count[23].CLK
clk => count[24].CLK
clk => count[25].CLK
clk => count[26].CLK
clk => count[27].CLK
clk => count[28].CLK
clk => count[29].CLK
clk => count[30].CLK
clk => count[31].CLK
reset_n => overflow~reg0.ACLR
reset_n => count[0].ACLR
reset_n => count[1].ACLR
reset_n => count[2].ACLR
reset_n => count[3].ACLR
reset_n => count[4].ACLR
reset_n => count[5].ACLR
reset_n => count[6].ACLR
reset_n => count[7].ACLR
reset_n => count[8].ACLR
reset_n => count[9].ACLR
reset_n => count[10].ACLR
reset_n => count[11].ACLR
reset_n => count[12].ACLR
reset_n => count[13].ACLR
reset_n => count[14].ACLR
reset_n => count[15].ACLR
reset_n => count[16].ACLR
reset_n => count[17].ACLR
reset_n => count[18].ACLR
reset_n => count[19].ACLR
reset_n => count[20].ACLR
reset_n => count[21].ACLR
reset_n => count[22].ACLR
reset_n => count[23].ACLR
reset_n => count[24].ACLR
reset_n => count[25].ACLR
reset_n => count[26].ACLR
reset_n => count[27].ACLR
reset_n => count[28].ACLR
reset_n => count[29].ACLR
reset_n => count[30].ACLR
reset_n => count[31].ACLR
ce => overflow~reg0.ENA
ce => count[0].ENA
ce => count[1].ENA
ce => count[2].ENA
ce => count[3].ENA
ce => count[4].ENA
ce => count[5].ENA
ce => count[6].ENA
ce => count[7].ENA
ce => count[8].ENA
ce => count[9].ENA
ce => count[10].ENA
ce => count[11].ENA
ce => count[12].ENA
ce => count[13].ENA
ce => count[14].ENA
ce => count[15].ENA
ce => count[16].ENA
ce => count[17].ENA
ce => count[18].ENA
ce => count[19].ENA
ce => count[20].ENA
ce => count[21].ENA
ce => count[22].ENA
ce => count[23].ENA
ce => count[24].ENA
ce => count[25].ENA
ce => count[26].ENA
ce => count[27].ENA
ce => count[28].ENA
ce => count[29].ENA
ce => count[30].ENA
ce => count[31].ENA
overflow <= overflow~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|switch:U_CounterClkSwitch
din1 => dout~0.DATAB
din2 => dout~0.DATAA
sel => dout~0.OUTPUTSELECT
dout <= dout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|detector:U_Detector
clk => new_data~reg0.CLK
clk => state.CLK
reset_n => new_data~reg0.ACLR
reset_n => state.ACLR
RxD => main~0.IN1
new_data <= new_data~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|parity_verifier:U_ParityVerifier
source[0] => ~NO_FANOUT~
source[1] => ~NO_FANOUT~
source[2] => ~NO_FANOUT~
source[3] => ~NO_FANOUT~
source[4] => ~NO_FANOUT~
source[5] => ~NO_FANOUT~
source[6] => ~NO_FANOUT~
source[7] => ~NO_FANOUT~
parity <= <VCC>


|uart_top|switch:U_SISwitch
din1 => dout~0.DATAB
din2 => dout~0.DATAA
sel => dout~0.OUTPUTSELECT
dout <= dout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|shift_register:U_SR
clk => shift_regs[0].CLK
clk => shift_regs[1].CLK
clk => shift_regs[2].CLK
clk => shift_regs[3].CLK
clk => shift_regs[4].CLK
clk => shift_regs[5].CLK
clk => shift_regs[6].CLK
clk => shift_regs[7].CLK
clk => shift_regs[8].CLK
clk => shift_regs[9].CLK
clk => dout~reg0.CLK
reset_n => dout~reg0.PRESET
reset_n => shift_regs[0].ENA
reset_n => shift_regs[1].ENA
reset_n => shift_regs[2].ENA
reset_n => shift_regs[3].ENA
reset_n => shift_regs[4].ENA
reset_n => shift_regs[5].ENA
reset_n => shift_regs[6].ENA
reset_n => shift_regs[7].ENA
reset_n => shift_regs[8].ENA
reset_n => shift_regs[9].ENA
din => shift_regs[0].DATAIN
regs[0] <= shift_regs[0].DB_MAX_OUTPUT_PORT_TYPE
regs[1] <= shift_regs[1].DB_MAX_OUTPUT_PORT_TYPE
regs[2] <= shift_regs[2].DB_MAX_OUTPUT_PORT_TYPE
regs[3] <= shift_regs[3].DB_MAX_OUTPUT_PORT_TYPE
regs[4] <= shift_regs[4].DB_MAX_OUTPUT_PORT_TYPE
regs[5] <= shift_regs[5].DB_MAX_OUTPUT_PORT_TYPE
regs[6] <= shift_regs[6].DB_MAX_OUTPUT_PORT_TYPE
regs[7] <= shift_regs[7].DB_MAX_OUTPUT_PORT_TYPE
regs[8] <= shift_regs[8].DB_MAX_OUTPUT_PORT_TYPE
regs[9] <= shift_regs[9].DB_MAX_OUTPUT_PORT_TYPE
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|switch:U_SRClkSwitch
din1 => dout~0.DATAB
din2 => dout~0.DATAA
sel => dout~0.OUTPUTSELECT
dout <= dout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|switch:U_TXDSwitch
din1 => dout~0.DATAB
din2 => dout~0.DATAA
sel => dout~0.OUTPUTSELECT
dout <= dout~0.DB_MAX_OUTPUT_PORT_TYPE