uart_top.tan.qmsg

实现FPGA和上位机的串口通信

{ "Info" "ITDB_TSU_RESULT" "uart_core:U_Core\|si_count\[2\] send clk 8.649 ns register " "Info: tsu for register \"uart_core:U_Core\|si_count\[2\]\" (data pin = \"send\", clock pin = \"clk\") is 8.649 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.799 ns + Longest pin register " "Info: + Longest pin to register delay is 11.799 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns send 1 PIN PIN_234 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_234; Fanout = 9; PIN Node = 'send'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { send } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.108 ns) + CELL(0.590 ns) 10.173 ns uart_core:U_Core\|si_count\[3\]~332 2 COMB LC_X28_Y18_N0 4 " "Info: 2: + IC(8.108 ns) + CELL(0.590 ns) = 10.173 ns; Loc. = LC_X28_Y18_N0; Fanout = 4; COMB Node = 'uart_core:U_Core\|si_count\[3\]~332'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.698 ns" { send uart_core:U_Core|si_count[3]~332 } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.759 ns) + CELL(0.867 ns) 11.799 ns uart_core:U_Core\|si_count\[2\] 3 REG LC_X27_Y18_N6 4 " "Info: 3: + IC(0.759 ns) + CELL(0.867 ns) = 11.799 ns; Loc. = LC_X27_Y18_N6; Fanout = 4; REG Node = 'uart_core:U_Core\|si_count\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.626 ns" { uart_core:U_Core|si_count[3]~332 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.932 ns ( 24.85 % ) " "Info: Total cell delay = 2.932 ns ( 24.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.867 ns ( 75.15 % ) " "Info: Total interconnect delay = 8.867 ns ( 75.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.799 ns" { send uart_core:U_Core|si_count[3]~332 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.799 ns" { send send~out0 uart_core:U_Core|si_count[3]~332 uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 8.108ns 0.759ns } { 0.000ns 1.475ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.187 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 348 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 348; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.711 ns) 3.187 ns uart_core:U_Core\|si_count\[2\] 2 REG LC_X27_Y18_N6 4 " "Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X27_Y18_N6; Fanout = 4; REG Node = 'uart_core:U_Core\|si_count\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.718 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.40 % ) " "Info: Total cell delay = 2.180 ns ( 68.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.60 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clk clk~out0 uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.799 ns" { send uart_core:U_Core|si_count[3]~332 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.799 ns" { send send~out0 uart_core:U_Core|si_count[3]~332 uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 8.108ns 0.759ns } { 0.000ns 1.475ns 0.590ns 0.867ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clk clk~out0 uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk TxD shift_register:U_SR\|dout 17.416 ns register " "Info: tco from clock \"clk\" to destination pin \"TxD\" through register \"shift_register:U_SR\|dout\" is 17.416 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.358 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 348 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 348; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.935 ns) 3.411 ns uart_core:U_Core\|sel_clk 2 REG LC_X28_Y18_N8 3 " "Info: 2: + IC(1.007 ns) + CELL(0.935 ns) = 3.411 ns; Loc. = LC_X28_Y18_N8; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.084 ns) + CELL(0.114 ns) 5.609 ns switch:U_SRClkSwitch\|dout~22 3 COMB LC_X23_Y13_N8 11 " "Info: 3: + IC(2.084 ns) + CELL(0.114 ns) = 5.609 ns; Loc. = LC_X23_Y13_N8; Fanout = 11; COMB Node = 'switch:U_SRClkSwitch\|dout~22'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.198 ns" { uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 } "NODE_NAME" } } { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.038 ns) + CELL(0.711 ns) 11.358 ns shift_register:U_SR\|dout 4 REG LC_X21_Y15_N8 1 " "Info: 4: + IC(5.038 ns) + CELL(0.711 ns) = 11.358 ns; Loc. = LC_X21_Y15_N8; Fanout = 1; REG Node = 'shift_register:U_SR\|dout'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.749 ns" { switch:U_SRClkSwitch|dout~22 shift_register:U_SR|dout } "NODE_NAME" } } { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 28.43 % ) " "Info: Total cell delay = 3.229 ns ( 28.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.129 ns ( 71.57 % ) " "Info: Total interconnect delay = 8.129 ns ( 71.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.358 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|dout } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.358 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|dout } { 0.000ns 0.000ns 1.007ns 2.084ns 5.038ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.834 ns + Longest register pin " "Info: + Longest register to pin delay is 5.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_register:U_SR\|dout 1 REG LC_X21_Y15_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y15_N8; Fanout = 1; REG Node = 'shift_register:U_SR\|dout'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_register:U_SR|dout } "NODE_NAME" } } { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 0.378 ns switch:U_TXDSwitch\|dout~2 2 COMB LC_X21_Y15_N8 3 " "Info: 2: + IC(0.000 ns) + CELL(0.378 ns) = 0.378 ns; Loc. = LC_X21_Y15_N8; Fanout = 3; COMB Node = 'switch:U_TXDSwitch\|dout~2'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.378 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 } "NODE_NAME" } } { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.348 ns) + CELL(2.108 ns) 5.834 ns TxD 3 PIN PIN_219 0 " "Info: 3: + IC(3.348 ns) + CELL(2.108 ns) = 5.834 ns; Loc. = PIN_219; Fanout = 0; PIN Node = 'TxD'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.456 ns" { switch:U_TXDSwitch|dout~2 TxD } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.486 ns ( 42.61 % ) " "Info: Total cell delay = 2.486 ns ( 42.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.348 ns ( 57.39 % ) " "Info: Total interconnect delay = 3.348 ns ( 57.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.834 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.834 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } { 0.000ns 0.000ns 3.348ns } { 0.000ns 0.378ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.358 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|dout } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.358 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|dout } { 0.000ns 0.000ns 1.007ns 2.084ns 5.038ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.834 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.834 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } { 0.000ns 0.000ns 3.348ns } { 0.000ns 0.378ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 100.00 % ) " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}