uart_top.tan.qmsg

实现FPGA和上位机的串口通信

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP memory sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|ram_block1a4~portb_address_reg0 register sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[7\] 141.62 MHz 7.061 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 141.62 MHz between source memory \"sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|ram_block1a4~portb_address_reg0\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[7\]\" (period= 7.061 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.332 ns + Longest memory register " "Info: + Longest memory to register delay is 6.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|ram_block1a4~portb_address_reg0 1 MEM M4K_X19_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y16; Fanout = 4; MEM Node = 'sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|ram_block1a4~portb_address_reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_9mi2.tdf" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/db/altsyncram_9mi2.tdf" 168 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|q_b\[7\] 2 MEM M4K_X19_Y16 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.317 ns" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_9mi2.tdf" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/db/altsyncram_9mi2.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.478 ns) 6.332 ns sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[7\] 3 REG LC_X15_Y13_N9 1 " "Info: 3: + IC(1.537 ns) + CELL(0.478 ns) = 6.332 ns; Loc. = LC_X15_Y13_N9; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|q_b[7] sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.795 ns ( 75.73 % ) " "Info: Total cell delay = 4.795 ns ( 75.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.537 ns ( 24.27 % ) " "Info: Total interconnect delay = 1.537 ns ( 24.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.332 ns" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|q_b[7] sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.332 ns" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|q_b[7] sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } { 0.000ns 0.000ns 1.537ns } { 0.000ns 4.317ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.042 ns - Smallest " "Info: - Smallest clock skew is -0.042 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.381 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 292 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 292; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.711 ns) 5.381 ns sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[7\] 2 REG LC_X15_Y13_N9 1 " "Info: 2: + IC(4.670 ns) + CELL(0.711 ns) = 5.381 ns; Loc. = LC_X15_Y13_N9; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.21 % ) " "Info: Total cell delay = 0.711 ns ( 13.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns ( 86.79 % ) " "Info: Total interconnect delay = 4.670 ns ( 86.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } { 0.000ns 4.670ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.423 ns - Longest memory " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source memory is 5.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 292 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 292; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.705 ns) + CELL(0.718 ns) 5.423 ns sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|ram_block1a4~portb_address_reg0 2 MEM M4K_X19_Y16 4 " "Info: 2: + IC(4.705 ns) + CELL(0.718 ns) = 5.423 ns; Loc. = M4K_X19_Y16; Fanout = 4; MEM Node = 'sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_9mi2:auto_generated\|ram_block1a4~portb_address_reg0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_9mi2.tdf" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/db/altsyncram_9mi2.tdf" 168 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.718 ns ( 13.24 % ) " "Info: Total cell delay = 0.718 ns ( 13.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.705 ns ( 86.76 % ) " "Info: Total interconnect delay = 4.705 ns ( 86.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } { 0.000ns 4.705ns } { 0.000ns 0.718ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } { 0.000ns 4.670ns } { 0.000ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } { 0.000ns 4.705ns } { 0.000ns 0.718ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_9mi2.tdf" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/db/altsyncram_9mi2.tdf" 168 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.332 ns" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|q_b[7] sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.332 ns" { sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|q_b[7] sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } { 0.000ns 0.000ns 1.537ns } { 0.000ns 4.317ns 0.478ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.381 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[7] } { 0.000ns 4.670ns } { 0.000ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.423 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated|ram_block1a4~portb_address_reg0 } { 0.000ns 4.705ns } { 0.000ns 0.718ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "uart_core:U_Core\|sel_si shift_register:U_SR\|shift_regs\[0\] clk 6.796 ns " "Info: Found hold time violation between source  pin or register \"uart_core:U_Core\|sel_si\" and destination pin or register \"shift_register:U_SR\|shift_regs\[0\]\" for clock \"clk\" (Hold time is 6.796 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.147 ns + Largest " "Info: + Largest clock skew is 8.147 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.334 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 348 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 348; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.935 ns) 3.411 ns uart_core:U_Core\|sel_clk 2 REG LC_X28_Y18_N8 3 " "Info: 2: + IC(1.007 ns) + CELL(0.935 ns) = 3.411 ns; Loc. = LC_X28_Y18_N8; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.084 ns) + CELL(0.114 ns) 5.609 ns switch:U_SRClkSwitch\|dout~22 3 COMB LC_X23_Y13_N8 11 " "Info: 3: + IC(2.084 ns) + CELL(0.114 ns) = 5.609 ns; Loc. = LC_X23_Y13_N8; Fanout = 11; COMB Node = 'switch:U_SRClkSwitch\|dout~22'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.198 ns" { uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 } "NODE_NAME" } } { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.014 ns) + CELL(0.711 ns) 11.334 ns shift_register:U_SR\|shift_regs\[0\] 4 REG LC_X28_Y16_N0 2 " "Info: 4: + IC(5.014 ns) + CELL(0.711 ns) = 11.334 ns; Loc. = LC_X28_Y16_N0; Fanout = 2; REG Node = 'shift_register:U_SR\|shift_regs\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.725 ns" { switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 28.49 % ) " "Info: Total cell delay = 3.229 ns ( 28.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.105 ns ( 71.51 % ) " "Info: Total interconnect delay = 8.105 ns ( 71.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.334 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.334 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 1.007ns 2.084ns 5.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.187 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 348 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 348; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.711 ns) 3.187 ns uart_core:U_Core\|sel_si 2 REG LC_X28_Y16_N3 3 " "Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y16_N3; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_si'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.718 ns" { clk uart_core:U_Core|sel_si } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.40 % ) " "Info: Total cell delay = 2.180 ns ( 68.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.60 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clk uart_core:U_Core|sel_si } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clk clk~out0 uart_core:U_Core|sel_si } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.334 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.334 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 1.007ns 2.084ns 5.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clk uart_core:U_Core|sel_si } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clk clk~out0 uart_core:U_Core|sel_si } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.142 ns - Shortest register register " "Info: - Shortest register to register delay is 1.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_core:U_Core\|sel_si 1 REG LC_X28_Y16_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y16_N3; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_si'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_core:U_Core|sel_si } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.535 ns) + CELL(0.607 ns) 1.142 ns shift_register:U_SR\|shift_regs\[0\] 2 REG LC_X28_Y16_N0 2 " "Info: 2: + IC(0.535 ns) + CELL(0.607 ns) = 1.142 ns; Loc. = LC_X28_Y16_N0; Fanout = 2; REG Node = 'shift_register:U_SR\|shift_regs\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { uart_core:U_Core|sel_si shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 53.15 % ) " "Info: Total cell delay = 0.607 ns ( 53.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.535 ns ( 46.85 % ) " "Info: Total interconnect delay = 0.535 ns ( 46.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { uart_core:U_Core|sel_si shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.142 ns" { uart_core:U_Core|sel_si shift_register:U_SR|shift_regs[0] } { 0.000ns 0.535ns } { 0.000ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "shift_register.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.334 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.334 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout~22 shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 1.007ns 2.084ns 5.014ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clk uart_core:U_Core|sel_si } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clk clk~out0 uart_core:U_Core|sel_si } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { uart_core:U_Core|sel_si shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.142 ns" { uart_core:U_Core|sel_si shift_register:U_SR|shift_regs[0] } { 0.000ns 0.535ns } { 0.000ns 0.607ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}