uart_top.tan.qmsg

实现FPGA和上位机的串口通信

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "baudrate_generator:U_BG\|bg_out " "Info: Detected ripple clock \"baudrate_generator:U_BG\|bg_out\" as buffer" {  } { { "baudrate_generator.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/baudrate_generator.vhd" 17 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "baudrate_generator:U_BG\|bg_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "switch:U_SRClkSwitch\|dout~22 " "Info: Detected gated clock \"switch:U_SRClkSwitch\|dout~22\" as buffer" {  } { { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 10 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "switch:U_SRClkSwitch\|dout~22" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baudrate_generator:U_BG\|indicator " "Info: Detected ripple clock \"baudrate_generator:U_BG\|indicator\" as buffer" {  } { { "baudrate_generator.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/baudrate_generator.vhd" 18 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "baudrate_generator:U_BG\|indicator" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_core:U_Core\|sel_clk " "Info: Detected ripple clock \"uart_core:U_Core\|sel_clk\" as buffer" {  } { { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 29 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "uart_core:U_Core\|sel_clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "switch:U_CounterClkSwitch\|dout~10 " "Info: Detected gated clock \"switch:U_CounterClkSwitch\|dout~10\" as buffer" {  } { { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 10 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "switch:U_CounterClkSwitch\|dout~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter:U_Counter\|overflow register uart_core:U_Core\|recv_bus\[0\] 82.45 MHz 12.128 ns Internal " "Info: Clock \"clk\" has Internal fmax of 82.45 MHz between source register \"counter:U_Counter\|overflow\" and destination register \"uart_core:U_Core\|recv_bus\[0\]\" (period= 12.128 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.453 ns + Longest register register " "Info: + Longest register to register delay is 3.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:U_Counter\|overflow 1 REG LC_X29_Y18_N8 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y18_N8; Fanout = 12; REG Node = 'counter:U_Counter\|overflow'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter:U_Counter|overflow } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/counter.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.341 ns) + CELL(0.114 ns) 1.455 ns uart_core:U_Core\|Selector11~16 2 COMB LC_X28_Y15_N5 8 " "Info: 2: + IC(1.341 ns) + CELL(0.114 ns) = 1.455 ns; Loc. = LC_X28_Y15_N5; Fanout = 8; COMB Node = 'uart_core:U_Core\|Selector11~16'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.455 ns" { counter:U_Counter|overflow uart_core:U_Core|Selector11~16 } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.867 ns) 3.453 ns uart_core:U_Core\|recv_bus\[0\] 3 REG LC_X29_Y15_N9 3 " "Info: 3: + IC(1.131 ns) + CELL(0.867 ns) = 3.453 ns; Loc. = LC_X29_Y15_N9; Fanout = 3; REG Node = 'uart_core:U_Core\|recv_bus\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.998 ns" { uart_core:U_Core|Selector11~16 uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.981 ns ( 28.41 % ) " "Info: Total cell delay = 0.981 ns ( 28.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.472 ns ( 71.59 % ) " "Info: Total interconnect delay = 2.472 ns ( 71.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.453 ns" { counter:U_Counter|overflow uart_core:U_Core|Selector11~16 uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.453 ns" { counter:U_Counter|overflow uart_core:U_Core|Selector11~16 uart_core:U_Core|recv_bus[0] } { 0.000ns 1.341ns 1.131ns } { 0.000ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.414 ns - Smallest " "Info: - Smallest clock skew is -8.414 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.178 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 348 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 348; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns uart_core:U_Core\|recv_bus\[0\] 2 REG LC_X29_Y15_N9 3 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X29_Y15_N9; Fanout = 3; REG Node = 'uart_core:U_Core\|recv_bus\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clk uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk clk~out0 uart_core:U_Core|recv_bus[0] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.592 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 11.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 348 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 348; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.935 ns) 3.411 ns uart_core:U_Core\|sel_clk 2 REG LC_X28_Y18_N8 3 " "Info: 2: + IC(1.007 ns) + CELL(0.935 ns) = 3.411 ns; Loc. = LC_X28_Y18_N8; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.101 ns) + CELL(0.442 ns) 6.954 ns switch:U_CounterClkSwitch\|dout~10 3 COMB LC_X11_Y13_N9 33 " "Info: 3: + IC(3.101 ns) + CELL(0.442 ns) = 6.954 ns; Loc. = LC_X11_Y13_N9; Fanout = 33; COMB Node = 'switch:U_CounterClkSwitch\|dout~10'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.543 ns" { uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 } "NODE_NAME" } } { "switch.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.927 ns) + CELL(0.711 ns) 11.592 ns counter:U_Counter\|overflow 4 REG LC_X29_Y18_N8 12 " "Info: 4: + IC(3.927 ns) + CELL(0.711 ns) = 11.592 ns; Loc. = LC_X29_Y18_N8; Fanout = 12; REG Node = 'counter:U_Counter\|overflow'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.638 ns" { switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } "NODE_NAME" } } { "counter.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/counter.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.557 ns ( 30.68 % ) " "Info: Total cell delay = 3.557 ns ( 30.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.035 ns ( 69.32 % ) " "Info: Total interconnect delay = 8.035 ns ( 69.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.592 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.592 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } { 0.000ns 0.000ns 1.007ns 3.101ns 3.927ns } { 0.000ns 1.469ns 0.935ns 0.442ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk clk~out0 uart_core:U_Core|recv_bus[0] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.592 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.592 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } { 0.000ns 0.000ns 1.007ns 3.101ns 3.927ns } { 0.000ns 1.469ns 0.935ns 0.442ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/counter.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "uart_core.vhd" "" { Text "C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.453 ns" { counter:U_Counter|overflow uart_core:U_Core|Selector11~16 uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.453 ns" { counter:U_Counter|overflow uart_core:U_Core|Selector11~16 uart_core:U_Core|recv_bus[0] } { 0.000ns 1.341ns 1.131ns } { 0.000ns 0.114ns 0.867ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk uart_core:U_Core|recv_bus[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk clk~out0 uart_core:U_Core|recv_bus[0] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.592 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.592 ns" { clk clk~out0 uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout~10 counter:U_Counter|overflow } { 0.000ns 0.000ns 1.007ns 3.101ns 3.927ns } { 0.000ns 1.469ns 0.935ns 0.442ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}