📄 uart_top.map.rpt
字号:
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+
; baudrate_generator.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/baudrate_generator.vhd ;
; counter.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/counter.vhd ;
; detector.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/detector.vhd ;
; parity_verifier.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/parity_verifier.vhd ;
; shift_register.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/shift_register.vhd ;
; switch.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/switch.vhd ;
; switch_bus.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/switch_bus.vhd ;
; uart_core.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/uart_core.vhd ;
; UART_PACKAGE.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/UART_PACKAGE.vhd ;
; uart_top.vhd ; yes ; User VHDL File ; C:/altera/70/qdesigns/PROGRAM/UART/uart_top.vhd ;
; sld_signaltap.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_signaltap.vhd ;
; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_shiftreg.tdf ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_constant.inc ;
; dffeea.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/dffeea.inc ;
; aglobal70.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/aglobal70.inc ;
; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_mbpmg.vhd ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_counter.inc ;
; alt_synch_counter.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_g9j.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/cntr_g9j.tdf ;
; db/cntr_fii.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/cntr_fii.tdf ;
; lpm_compare.tdf ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_compare.tdf ;
; comptree.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/comptree.inc ;
; altshift.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/altshift.inc ;
; db/cmpr_fnh.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/cmpr_fnh.tdf ;
; sld_acquisition_buffer.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_acquisition_buffer.vhd ;
; db/cntr_hek.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/cntr_hek.tdf ;
; lpm_ff.tdf ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_ff.tdf ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_mux.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_9mi2.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/altsyncram_9mi2.tdf ;
; db/cntr_dfh.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/cntr_dfh.tdf ;
; db/cntr_78i.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/cntr_78i.tdf ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_rom_sr.vhd ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_hub.vhd ;
; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/lpm_decode.tdf ;
; declut.inc ; yes ; Megafunction ; c:/altera/70/quartus/libraries/megafunctions/declut.inc ;
; db/decode_ogi.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/70/qdesigns/PROGRAM/UART/db/decode_ogi.tdf ;
; sld_dffex.vhd ; yes ; Encrypted Megafunction ; c:/altera/70/quartus/libraries/megafunctions/sld_dffex.vhd ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+
+----------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------------+
; Total logic elements ; 188 ;
; -- Combinational with no register ; 97 ;
; -- Register only ; 40 ;
; -- Combinational with a register ; 51 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 48 ;
; -- 3 input functions ; 14 ;
; -- 2 input functions ; 63 ;
; -- 1 input functions ; 23 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 142 ;
; -- arithmetic mode ; 46 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 81 ;
; ; ;
; Total registers ; 91 ;
; Total logic cells in carry chains ; 48 ;
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