uart_top.map.rpt

实现FPGA和上位机的串口通信

Analysis & Synthesis report for uart_top
Mon Dec 29 15:50:29 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |uart_top|uart_core:U_Core|state
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for sld_signaltap:auto_signaltap_0
 12. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_9mi2:auto_generated
 13. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 14. Source assignments for sld_hub:sld_hub_inst
 15. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 16. Parameter Settings for User Entity Instance: Top-level Entity: |uart_top
 17. Parameter Settings for User Entity Instance: baudrate_generator:U_BG
 18. Parameter Settings for User Entity Instance: switch_bus:U_BusSwitch
 19. Parameter Settings for User Entity Instance: uart_core:U_Core
 20. Parameter Settings for User Entity Instance: counter:U_Counter
 21. Parameter Settings for User Entity Instance: parity_verifier:U_ParityVerifier
 22. Parameter Settings for User Entity Instance: shift_register:U_SR
 23. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 24. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 25. SignalTap II Logic Analyzer Settings
 26. Analysis & Synthesis Resource Utilization by Entity
 27. Analysis & Synthesis Resource Utilization by Entity
 28. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Dec 29 15:50:29 2008   ;
; Quartus II Version          ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name               ; uart_top                                ;
; Top-level Entity Name       ; uart_top                                ;
; Family                      ; Cyclone                                 ;
; Total logic elements        ; N/A until Partition Merge               ;
; Total pins                  ; N/A until Partition Merge               ;
; Total virtual pins          ; N/A until Partition Merge               ;
; Total memory bits           ; N/A until Partition Merge               ;
; Total PLLs                  ; N/A until Partition Merge               ;
+-----------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C12Q240C8       ;                    ;
; Top-level entity name                                              ; uart_top           ; uart_top           ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                  ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;