stp1.stp

实现FPGA和上位机的串口通信

<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP1C12 (0x020830DD)" sof_file="" top_level_entity="uart_top">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance compilation_mode="incremental" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="5"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2008/12/29 14:54:33  #0">
      <clock name="clk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="RxD" tap_mode="probeonly" type="input pin"/>
          <wire name="TxD" tap_mode="probeonly" type="output pin"/>
          <wire name="error" tap_mode="probeonly" type="output pin"/>
          <wire name="recv" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[0]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[1]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[2]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[3]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[4]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[5]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[6]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[7]" tap_mode="probeonly" type="output pin"/>
          <wire name="reset_n" tap_mode="probeonly" type="input pin"/>
          <wire name="send" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[0]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[1]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[2]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[3]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[4]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[5]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[6]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[7]" tap_mode="probeonly" type="input pin"/>
          <wire name="send_over" tap_mode="probeonly" type="output pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="RxD" tap_mode="probeonly" type="input pin"/>
          <wire name="TxD" tap_mode="probeonly" type="output pin"/>
          <wire name="error" tap_mode="probeonly" type="output pin"/>
          <wire name="recv" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[0]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[1]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[2]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[3]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[4]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[5]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[6]" tap_mode="probeonly" type="output pin"/>
          <wire name="recv_bus[7]" tap_mode="probeonly" type="output pin"/>
          <wire name="reset_n" tap_mode="probeonly" type="input pin"/>
          <wire name="send" tap_mode="probeonly" type="input pin"/>
          <wire name="send_bus[0]" tap_mode="probeonly" type="input pin"/>