uart_top.tan.rpt

实现FPGA和上位机的串口通信

; Clock Hold: 'clk'                           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; uart_core:U_Core|sel_si                                                                                                                       ; shift_register:U_SR|shift_regs[0]                                                                                                                       ; clk                          ; clk                          ; 531          ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                                                                                                                               ;                                                                                                                                                         ;                              ;                              ; 531          ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk                          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                        ; To                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 82.45 MHz ( period = 12.128 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[0]                         ; clk        ; clk      ; None                        ; None                      ; 3.453 ns                ;
; N/A                                     ; 82.45 MHz ( period = 12.128 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[1]                         ; clk        ; clk      ; None                        ; None                      ; 3.453 ns                ;
; N/A                                     ; 82.45 MHz ( period = 12.128 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[2]                         ; clk        ; clk      ; None                        ; None                      ; 3.453 ns                ;
; N/A                                     ; 82.45 MHz ( period = 12.128 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[3]                         ; clk        ; clk      ; None                        ; None                      ; 3.453 ns                ;
; N/A                                     ; 82.45 MHz ( period = 12.128 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|recv_bus[4]                         ; clk        ; clk      ; None                        ; None                      ; 3.453 ns                ;
; N/A                                     ; 84.42 MHz ( period = 11.845 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|sel_out                             ; clk        ; clk      ; None                        ; None                      ; 3.170 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|si_count[2]                         ; clk        ; clk      ; None                        ; None                      ; 3.134 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:U_Counter|overflow                  ; uart_core:U_Core|si_count[1]                         ; clk        ; clk      ; None                        ; None                      ; 3.134 ns                ;