uart_top.sim.rpt

实现FPGA和上位机的串口通信

; |baudrate_generator|Add0~261            ; |baudrate_generator|Add0~262COUT1       ; cout1            ;
; |baudrate_generator|Add0~263            ; |baudrate_generator|Add0~263            ; combout          ;
; |baudrate_generator|Add0~263            ; |baudrate_generator|Add0~264            ; cout0            ;
; |baudrate_generator|Add0~265            ; |baudrate_generator|Add0~265            ; combout          ;
; |baudrate_generator|Add0~265            ; |baudrate_generator|Add0~266            ; cout0            ;
; |baudrate_generator|Add0~268            ; |baudrate_generator|Add0~268            ; cout0            ;
; |baudrate_generator|Add0~268            ; |baudrate_generator|Add0~268COUT1       ; cout1            ;
; |baudrate_generator|\main:clk_count[7]  ; |baudrate_generator|\main:clk_count[7]  ; regout           ;
; |baudrate_generator|\main:clk_count[8]  ; |baudrate_generator|\main:clk_count[8]  ; regout           ;
; |baudrate_generator|Equal0~137          ; |baudrate_generator|Equal0~137          ; combout          ;
; |baudrate_generator|\main:clk_count[12] ; |baudrate_generator|\main:clk_count[12] ; regout           ;
; |baudrate_generator|\main:clk_count[2]  ; |baudrate_generator|\main:clk_count[2]  ; regout           ;
; |baudrate_generator|\main:clk_count[4]  ; |baudrate_generator|\main:clk_count[4]  ; regout           ;
; |baudrate_generator|\main:clk_count[6]  ; |baudrate_generator|\main:clk_count[6]  ; regout           ;
; |baudrate_generator|\main:clk_count[10] ; |baudrate_generator|\main:clk_count[10] ; regout           ;
; |baudrate_generator|Equal0~138          ; |baudrate_generator|Equal0~138          ; combout          ;
; |baudrate_generator|Equal0~139          ; |baudrate_generator|Equal0~139          ; combout          ;
; |baudrate_generator|\main:clk_count[0]  ; |baudrate_generator|\main:clk_count[0]  ; regout           ;
; |baudrate_generator|\main:clk_count[1]  ; |baudrate_generator|\main:clk_count[1]  ; regout           ;
; |baudrate_generator|\main:clk_count[3]  ; |baudrate_generator|\main:clk_count[3]  ; regout           ;
; |baudrate_generator|\main:clk_count[5]  ; |baudrate_generator|\main:clk_count[5]  ; regout           ;
; |baudrate_generator|Equal0~140          ; |baudrate_generator|Equal0~140          ; combout          ;
; |baudrate_generator|\main:clk_count[9]  ; |baudrate_generator|\main:clk_count[9]  ; regout           ;
; |baudrate_generator|\main:clk_count[11] ; |baudrate_generator|\main:clk_count[11] ; regout           ;
; |baudrate_generator|Equal0~141          ; |baudrate_generator|Equal0~141          ; combout          ;
; |baudrate_generator|indicator~217       ; |baudrate_generator|indicator~217       ; combout          ;
; |baudrate_generator|Equal1~92           ; |baudrate_generator|Equal1~92           ; combout          ;
; |baudrate_generator|Equal1~93           ; |baudrate_generator|Equal1~93           ; combout          ;
; |baudrate_generator|indicator~218       ; |baudrate_generator|indicator~218       ; combout          ;
; |baudrate_generator|clk                 ; |baudrate_generator|clk                 ; combout          ;
+-----------------------------------------+-----------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                   ;
+------------------------------------+------------------------------------+------------------+
; Node Name                          ; Output Port Name                   ; Output Port Type ;
+------------------------------------+------------------------------------+------------------+
; |baudrate_generator|Add0~241       ; |baudrate_generator|Add0~242COUT1  ; cout1            ;
; |baudrate_generator|Add0~243       ; |baudrate_generator|Add0~244       ; cout0            ;
; |baudrate_generator|Add0~245       ; |baudrate_generator|Add0~246       ; cout0            ;
; |baudrate_generator|Add0~245       ; |baudrate_generator|Add0~246COUT1  ; cout1            ;
; |baudrate_generator|Add0~247       ; |baudrate_generator|Add0~248       ; cout             ;
; |baudrate_generator|Add0~251       ; |baudrate_generator|Add0~252       ; cout0            ;
; |baudrate_generator|Add0~253       ; |baudrate_generator|Add0~254       ; cout0            ;
; |baudrate_generator|Add0~255       ; |baudrate_generator|Add0~256COUT1  ; cout1            ;
; |baudrate_generator|Add0~259       ; |baudrate_generator|Add0~260       ; cout0            ;
; |baudrate_generator|Add0~261       ; |baudrate_generator|Add0~262       ; cout0            ;
; |baudrate_generator|Add0~263       ; |baudrate_generator|Add0~264COUT1  ; cout1            ;
; |baudrate_generator|Add0~265       ; |baudrate_generator|Add0~266COUT1  ; cout1            ;
; |baudrate_generator|indicator~reg0 ; |baudrate_generator|indicator~reg0 ; regout           ;
; |baudrate_generator|Equal1~94      ; |baudrate_generator|Equal1~94      ; combout          ;
; |baudrate_generator|indicator~219  ; |baudrate_generator|indicator~219  ; combout          ;
; |baudrate_generator|indicator      ; |baudrate_generator|indicator      ; padio            ;
; |baudrate_generator|reset_n        ; |baudrate_generator|reset_n        ; combout          ;
; |baudrate_generator|ce             ; |baudrate_generator|ce             ; combout          ;
+------------------------------------+------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                             ;
+-----------------------------------------+-----------------------------------------+------------------+
; Node Name                               ; Output Port Name                        ; Output Port Type ;
+-----------------------------------------+-----------------------------------------+------------------+
; |baudrate_generator|Add0~241            ; |baudrate_generator|Add0~242COUT1       ; cout1            ;
; |baudrate_generator|Add0~243            ; |baudrate_generator|Add0~244            ; cout0            ;
; |baudrate_generator|Add0~243            ; |baudrate_generator|Add0~244COUT1       ; cout1            ;
; |baudrate_generator|Add0~245            ; |baudrate_generator|Add0~246            ; cout0            ;
; |baudrate_generator|Add0~251            ; |baudrate_generator|Add0~252            ; cout0            ;
; |baudrate_generator|Add0~253            ; |baudrate_generator|Add0~254            ; cout0            ;
; |baudrate_generator|Add0~255            ; |baudrate_generator|Add0~256COUT1       ; cout1            ;
; |baudrate_generator|Add0~259            ; |baudrate_generator|Add0~260            ; cout0            ;
; |baudrate_generator|Add0~261            ; |baudrate_generator|Add0~262            ; cout0            ;
; |baudrate_generator|Add0~263            ; |baudrate_generator|Add0~264COUT1       ; cout1            ;
; |baudrate_generator|Add0~265            ; |baudrate_generator|Add0~266COUT1       ; cout1            ;
; |baudrate_generator|indicator~reg0      ; |baudrate_generator|indicator~reg0      ; regout           ;
; |baudrate_generator|\main:clk_count[15] ; |baudrate_generator|\main:clk_count[15] ; regout           ;
; |baudrate_generator|\main:clk_count[13] ; |baudrate_generator|\main:clk_count[13] ; regout           ;
; |baudrate_generator|\main:clk_count[14] ; |baudrate_generator|\main:clk_count[14] ; regout           ;
; |baudrate_generator|Equal1~94           ; |baudrate_generator|Equal1~94           ; combout          ;
; |baudrate_generator|indicator~219       ; |baudrate_generator|indicator~219       ; combout          ;
; |baudrate_generator|bg_out              ; |baudrate_generator|bg_out              ; padio            ;
; |baudrate_generator|indicator           ; |baudrate_generator|indicator           ; padio            ;
; |baudrate_generator|reset_n             ; |baudrate_generator|reset_n             ; combout          ;
; |baudrate_generator|ce                  ; |baudrate_generator|ce                  ; combout          ;
+-----------------------------------------+-----------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Dec 29 09:31:31 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off uart_top -c uart_top
Info: Using vector source file "C:/altera/70/qdesigns/PROGRAM/UART/baudrate_generator.vwf"
Info: Inverted registers were found during simulation
    Info: Register: |baudrate_generator|\main:clk_count[15]
    Info: Register: |baudrate_generator|\main:clk_count[7]
    Info: Register: |baudrate_generator|\main:clk_count[8]
    Info: Register: |baudrate_generator|\main:clk_count[13]
    Info: Register: |baudrate_generator|\main:clk_count[14]
    Info: Register: |baudrate_generator|\main:clk_count[12]
    Info: Register: |baudrate_generator|\main:clk_count[2]
    Info: Register: |baudrate_generator|\main:clk_count[4]
    Info: Register: |baudrate_generator|\main:clk_count[6]
    Info: Register: |baudrate_generator|\main:clk_count[10]
    Info: Register: |baudrate_generator|\main:clk_count[0]
    Info: Register: |baudrate_generator|\main:clk_count[1]
    Info: Register: |baudrate_generator|\main:clk_count[3]
    Info: Register: |baudrate_generator|\main:clk_count[5]
    Info: Register: |baudrate_generator|\main:clk_count[9]
    Info: Register: |baudrate_generator|\main:clk_count[11]
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      69.33 %
Info: Number of transitions in simulation is 68613
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 88 megabytes of memory during processing
    Info: Processing ended: Mon Dec 29 09:31:33 2008
    Info: Elapsed time: 00:00:02