uart_top.fit.summary

实现FPGA和上位机的串口通信

Fitter Status : Successful - Mon Dec 29 15:50:53 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : uart_top
Top-level Entity Name : uart_top
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Total logic elements : 682 / 12,060 ( 6 % )
Total pins : 28 / 173 ( 16 % )
Total virtual pins : 0
Total memory bits : 23,552 / 239,616 ( 10 % )
Total PLLs : 0 / 2 ( 0 % )