uart_top.fit.smsg

实现FPGA和上位机的串口通信

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Dec 29 15:50:36 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_top -c uart_top
Info: Selected device EP1C12Q240C8 for design "uart_top"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 3 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 217 of 217 atoms in partition Top
    Info: Previous placement does not exist for 455 of 455 atoms in partition sld_signaltap:auto_signaltap_0
    Info: Previous placement does not exist for 112 of 112 atoms in partition sld_hub:sld_hub_inst
Info: Detected 2 design partitions (excluding Top) used without floorplan location assignments.
    Info: Design partition sld_signaltap:auto_signaltap_0 has no floorplan location assignments
    Info: Design partition sld_hub:sld_hub_inst has no floorplan location assignments
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Warning: No exact pin location assignment(s) for 8 pins of 24 total pins
    Info: Pin send_bus[5] not assigned to an exact location on the device
    Info: Pin send_bus[4] not assigned to an exact location on the device
    Info: Pin send_bus[3] not assigned to an exact location on the device
    Info: Pin send_bus[6] not assigned to an exact location on the device
    Info: Pin send_bus[0] not assigned to an exact location on the device
    Info: Pin send_bus[7] not assigned to an exact location on the device
    Info: Pin send_bus[2] not assigned to an exact location on the device
    Info: Pin send_bus[1] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 28
    Info: Destination "switch:U_SRClkSwitch|dout~22" may be non-global or may not use global clock
    Info: Destination "switch:U_CounterClkSwitch|dout~10" may be non-global or may not use global clock
Info: Automatically promoted signal "altera_internal_jtag~TCKUTAP" to use Global clock
Info: Automatically promoted signal "switch:U_CounterClkSwitch|dout~10" to use Global clock
Info: Automatically promoted signal "switch:U_SRClkSwitch|dout~22" to use Global clock
Info: Automatically promoted some destinations of signal "sld_signaltap:auto_signaltap_0|reset_all" to use Global clock
    Info: Destination "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "uart_core:U_Core|reset_parts" to use Global clock
    Info: Destination "shift_register:U_SR|shift_regs[0]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[1]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[2]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[3]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[4]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[5]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[6]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[7]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[8]" may be non-global or may not use global clock
    Info: Destination "shift_register:U_SR|shift_regs[9]" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|CLR_SIGNAL" to use Global clock
    Info: Destination "sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "reset_n" to use Global clock
    Info: Destination "shift_register:U_SR|shift_regs[0]" may be non-global or may not use global clock
    Info: Destination "sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[12]" may be non-global or may not use global clock
    Info: Destination "sld_signaltap:auto_signaltap_0|acq_data_in_reg[12]" may be non-global or may not use global clock
Info: Pin "reset_n" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 8 input, 0 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  38 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  38 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  37 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 3.156 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X29_Y18; Fanout = 12; REG Node = 'counter:U_Counter|overflow'
    Info: 2: + IC(0.855 ns) + CELL(0.114 ns) = 0.969 ns; Loc. = LAB_X28_Y18; Fanout = 3; COMB Node = 'uart_core:U_Core|Selector0~180'
    Info: 3: + IC(0.539 ns) + CELL(0.114 ns) = 1.622 ns; Loc. = LAB_X28_Y18; Fanout = 4; COMB Node = 'uart_core:U_Core|si_count[3]~332'
    Info: 4: + IC(0.667 ns) + CELL(0.867 ns) = 3.156 ns; Loc. = LAB_X27_Y18; Fanout = 4; REG Node = 'uart_core:U_Core|si_count[2]'
    Info: Total cell delay = 1.095 ns ( 34.70 % )
    Info: Total interconnect delay = 2.061 ns ( 65.30 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 5%
    Info: The peak interconnect region extends from location X10_Y14 to location X20_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:05
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Node sld_signaltap:auto_signaltap_0|reset_all uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena -- routed using non-global resources
Info: Node uart_core:U_Core|reset_parts uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node counter:U_Counter|count[28] -- routed using non-global resources
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 184 megabytes of memory during processing
    Info: Processing ended: Mon Dec 29 15:50:53 2008
    Info: Elapsed time: 00:00:17