uart_top.map.summary

来自「实现FPGA和上位机的串口通信」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Mon Dec 29 15:50:29 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : uart_top
Top-level Entity Name : uart_top
Family : Cyclone
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge