top.vhd

RS232串行通信

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity top is
port (clk32,reset,rxd,xmit_cmd_p_in:in std_logic;
txdbuf_in:in std_logic_vector(7 downto 0);
rec_ready,txd_out,txd_done_out:out std_logic;
rec_buf:out std_logic_vector(7 downto 0));
end top;
architecture behavioral of top is

component receiver
port(bclkr,resetr,rxdr:in std_logic;
r_ready:out std_logic;
rbuf:out std_logic_vector(7 downto 0));
end component;

component transfer
port(bclkt,resett,xmit_cmd_p:in std_logic;
txd,txd_done:out std_logic;
txdbuf:in std_logic_vector(7 downto 0));
end component;

component baud
port(clk,resetb:in std_logic;
bclk:out std_logic);
end component;

signal b:std_logic;
begin 
u1:baud port map(clk=>clk32,resetb=>reset,bclk=>b);
u2:receiver port map(bclkr=>b,resetr=>reset,rxdr=>rxd,r_ready=>rec_ready,rbuf=>rec_buf);
u3:transfer port map(bclkt=>b,resett=>reset,xmit_cmd_p=>xmit_cmd_p_in,txdbuf=>txdbuf_in,txd=>txd_out,txd_done=>txd_done_out);
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity baud is
port (clk,resetb:in std_logic;
bclk:out std_logic);
end baud;
architecture behavioral of baud is
begin
process(clk,resetb)
variable cnt:integer;
begin 
if resetb='1' then
cnt:=0;bclk<='0';
elsif rising_edge(clk) then
if cnt>=208 then cnt:=0;bclk<='1';
else cnt:=cnt+1;bclk<='0';
end if;
end if;
end process;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity receiver is
generic (framlenr:integer:=8);
port(bclkr,resetr,rxdr:in std_logic;
r_ready:out std_logic;
rbuf:out std_logic_vector(7 downto 0));
end receiver;
architecture behavioral of receiver is
type states is (r_start,r_center,r_wait,r_sample,r_stop);
signal state:states:=r_start;
signal rxd_sync:std_logic;
begin
pro1:process(rxdr)
begin 
if rxdr='0' then
rxd_sync<='0';
else rxd_sync<='1';
end if;
end process;

pro2:process(bclkr,resetr,rxd_sync)
variable count:std_logic_vector(3 downto 0);
variable rcnt:integer:=0;
variable rbufs:std_logic_vector(7 downto 0);
begin 
if resetr='1' then
state<=r_start;count:="0000";
elsif rising_edge(bclkr) then
case state is
when r_start=>if rxd_sync='0' then
state<=r_center;r_ready<='0';rcnt:=0;
else state<=r_start;r_ready<='0';
end if;
when r_center=>if rxd_sync='0' then
if count="0100" then
state<=r_wait;count:="0000";
else state<=r_center;count:=count+1;
end if;
else state<=r_start;
end if;
when r_wait=>if count>="1110" then
if rcnt=framlenr then 
state<=r_stop;
else state<=r_sample;
end if;
count:="0000";
else state<=r_wait;count:=count+1;
end if;
when r_sample=>rbufs(rcnt):=rxd_sync; 
rcnt:=rcnt+1;state<=r_wait;
when r_stop=>r_ready<='1';rbuf<=rbufs; 
state<=r_start;
when others=>state<=r_start;
end case;
end if;
end process;
end behavioral;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity transfer is
generic(framlent:integer:=8);
port(bclkt,resett,xmit_cmd_p:in std_logic;
txd,txd_done:out std_logic;
txdbuf:in std_logic_vector(7 downto 0):="11001010");
end transfer;

architecture behavioral of transfer is
type states is (x_idle,x_start,x_wait,x_shift,x_stop);
signal state:states:=x_idle;
signal tcnt:integer:=0;
begin
process(bclkt,resett,xmit_cmd_p,txdbuf)
variable xcnt16:std_logic_vector(4 downto 0);
variable xbitcnt:integer:=0;
variable txds:std_logic;
begin 
if resett='1' then
state<=x_idle;txd_done<='0';txds:='1';
elsif rising_edge(bclkt) then
case state is
when x_idle=>if xmit_cmd_p='1' then
state<=x_start;txd_done<='0';
else state<=x_idle;
end if;
when x_start=>if xcnt16>="01111" then
state<=x_wait;xcnt16:="00000";
else xcnt16:=xcnt16+1;txds:='0';state<=x_start;
end if;
when x_wait=>if xcnt16>="01110" then
if xbitcnt=framlent then 
state<=x_stop;xbitcnt:=0;
else state<=x_shift;
end if;
xcnt16:="00000";
else xcnt16:=xcnt16+1;state<=x_wait;
end if;
when x_shift=>txds:=txdbuf(xbitcnt); 
xbitcnt:=xbitcnt+1;state<=x_wait;
when x_stop=>if xcnt16>="01111" then
if xmit_cmd_p='0' then
state<=x_idle;xcnt16:="00000";
else xcnt16:=xcnt16;state<=x_stop;
end if;
txd_done<='1';
else xcnt16:=xcnt16+1;txds:='1';state<=x_stop;
end if;
when others=>state<=x_idle;
end case;
end if;
txd<=txds;
end process;
end behavioral;