count6.vhd

来自「vhdl codes for combinational and sequent」· VHDL 代码 · 共 27 行

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    Entity countr is
    				port(
    						rst,clk : in std_logic;
    						out : out std_logic_vector(2 downto 0));
    			end countr;
    	architecture behaviour of countr is
    	signal temp,c1,c2 : std_logic_vector(2 downto 0);
    				begin	process(clk,rst)
    					begin
    						if (rst = '1') then
    							out <= "000";
    						elsif (clk'event and clk = '1' and c1 < "111") then
    							temp <= temp + "001";
    							out <= temp;
    							c1 <= c1 + "001";  							 							
    						elsif (clk'event and clk = '1' and c2 < "111") then)
    							temp <= temp + "001";
    							out <= temp;
    							c2 <= c2 + "001";
    							
    						end if;
    					end process;
    					end behaviour;