adder_full.vhd

来自「vhdl codes for combinational and sequent」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity f_add is 
port(
     a,b,c:in std_logic;
     o,co:out std_logic);
end f_add;

architecture bhv of f_add is 
begin
o<=a xor b xor c;
co<=(a and b)or(b and c)or(c and a);
end bhv;