jkff_tb.vhd

来自「vhdl codes for combinational and sequent」· VHDL 代码 · 共 37 行

library ieee;
    use ieee.std_logic_1164.all;
Entity JKFF_tb is
end JKFF_tb;
architecture bhv of JKff_tb is
    component JKFF is
         port(
        j,k:in std_logic;
        clk,reset:in std_logic;
        Q:out std_logic);
    end Component;
    signal j,k,clk,reset,Q:std_logic;
    begin
        p1:JKFF port map(j,k,clk,reset,Q);
    process
        begin
        clk<='1'; wait for 50 ns;
        clk<='0';wait for 50 ns;
    end process;
    process
         begin
        reset<='1'; wait for 1000 ns;
        reset<='0';wait for 1000 ns;
    end process;
    process
         begin
        j<='1'; wait for 500 ns;
        j<='0';wait for 500 ns;
    end process;
    process
         begin
        k<='1'; wait for 100 ns;
        k<='0';wait for 100 ns;
    end process;
    
end bhv;