jkff.vhd

vhdl codes for combinational and sequential circuit

library ieee;
    use ieee.std_logic_1164.all;
Entity JKFF is
    port(
        j,k:in std_logic;
        clk,reset:in std_logic;
        Q:out std_logic);
    end JKFF;  
Architecture bhv of JKFF is
    signal t:std_logic;
    begin
        process(reset,clk)
            begin
            if reset='1' then
                t<='0';
                elsif clk='1' and clk'event then
                  t<=(j and not(t)) or(not(k) and t);
                end if;
            end process;
            Q<=t;
        end bhv;