counter_tb.vhd

vhdl codes for combinational and sequential circuit

library ieee;
    use ieee.std_logic_1164.all;
    Entity Counter_tb is
    End Counter_tb;
    Architecture Bhv of Counter_tb is
        Component counter is
            port(
            clk1:in std_logic;
            reset1:in std_logic;
            Q2:out std_logic_vector(3 downto 0)
            );
        End component;
        signal clk1,reset1:std_logic;
        SIGNAL Q2:std_logic_vector(3 downto 0);
        begin
            P1:Counter port map(clk1,reset1,Q2);
            process
                begin
                    clk1<='1';wait for 50 ns;
                    clk1<='0';wait for 50 ns;
                end process;
                process
                    begin
                        reset1<='1';wait for 5000 ns;
                        reset1<='0';wait for 5000 ns;
                end process;
            end Bhv;