简单的锁存器.txt

来自「对微电子的学习和FPGA的开发设计很有帮助」· 文本 代码 · 共 28 行

-- Latch Inference
-- Download from: http://www.fpga.com.cn

Library IEEE ;
use IEEE.std_logic_1164.all ;

ENTITY latchinf IS
	PORT
	(
		enable, data	: IN BIT;
		q				: OUT BIT
	);
END latchinf;

ARCHITECTURE maxpld OF latchinf IS
BEGIN

latch :	PROCESS (enable, data)
		BEGIN
			IF (enable = '1') THEN
				q <= data;
			END IF;
		END PROCESS latch;

END maxpld;