📄 vgacore-optimized.trt
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======================
Chip vgacore-Optimized
======================
Summary Information:
--------------------
Type: Optimized implementation
Source: vgacore, up to date
Status: 0 errors, 0 warnings, 1 messages
Export: exported after last optimization
Target Information:
-------------------
Vendor: Xilinx
Family: XC4000
Device: 4005XLPC84
Speed: xl-3
Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: Low
Frequency: 50 MHz
Is module: Yes
Keep io pads: No
Number of flip-flops: 36
Number of latches: 0
Chip Design Hierarchy:
----------------------
vgacore: defined in F:\XESSCORP\ELASCOMP\XSBRDS\designs\VGAVHDL\vgacore.vhd
Primitive reference count:
--------------------------
BUFG 2
CY4 11
CY4_18 8
CY4_20 2
CY4_42 1
DFF 36
FMAP 45
HMAP 5
OBUF 2
STARTUP 1
Clocks:
-------
Required Estimated
Period Rise Fall Freq Freq Signal
(ns) (ns) (ns) (MHz) (MHz)
...............................................................
20 0 10 50.00 n/a default
n/a n/a n/a n/a 37.50 N374
n/a n/a n/a n/a 100.00 N375
Timing Groups:
--------------
Name Description
............................................................
(I) Input ports
(O) Output ports
(RC,N374) Clocked by rising edge of N374
(RC,N375) Clocked by rising edge of N375
Timing Path Groups:
-------------------
Required Estimated
Delay Delay
From To (ns) (ns)
............................................................
(I) (RC,N374) 20.00 8.05
(RC,N374) (O) 20.00 12.71
(RC,N374) (RC,N374) 20.00 26.67
(RC,N375) (O) 20.00 16.51
(RC,N375) (RC,N374) 20.00 17.01
(RC,N375) (RC,N375) 20.00 0.00
Input Port Timing:
------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) To-Group
............................................................
reset n/a n/a (RC,N374)
clock 11.95 11.95 (RC,N374)
data<7> 12.10 12.10 (RC,N374)
data<6> 12.10 12.10 (RC,N374)
data<5> 12.10 12.10 (RC,N374)
data<4> 12.10 12.10 (RC,N374)
data<3> 12.10 12.10 (RC,N374)
data<2> 12.10 12.10 (RC,N374)
data<1> 12.10 12.10 (RC,N374)
data<0> 12.10 12.10 (RC,N374)
Output Port Timing:
-------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) From-Group
............................................................
hsyncb 20.00 14.51 (RC,N374)
vsyncb 20.00 15.05 (RC,N374)
rgb<5> 20.00 15.05 (RC,N374)
rgb<4> 20.00 15.05 (RC,N374)
rgb<3> 20.00 15.05 (RC,N374)
rgb<2> 20.00 15.05 (RC,N374)
rgb<1> 20.00 15.05 (RC,N374)
rgb<0> 20.00 15.05 (RC,N374)
addr<14> 20.00 12.87 (RC,N374)
addr<13> 20.00 12.87 (RC,N374)
addr<12> 20.00 12.87 (RC,N374)
addr<11> 20.00 12.87 (RC,N374)
addr<10> 20.00 12.87 (RC,N374)
addr<9> 20.00 12.87 (RC,N374)
addr<8> 20.00 12.87 (RC,N374)
addr<7> 20.00 12.87 (RC,N374)
addr<6> 20.00 13.42 (RC,N374)
addr<5> 20.00 12.87 (RC,N374)
addr<4> 20.00 11.24 (RC,N374)
addr<3> 20.00 12.33 (RC,N374)
addr<2> 20.00 12.33 (RC,N374)
addr<1> 20.00 12.33 (RC,N374)
addr<0> 20.00 12.33 (RC,N374)
csb n/a n/a (RC,N374)
oeb 20.00 3.49 (RC,N374)
web n/a n/a (RC,N374)
Critical Path Timing:
---------------------
Arrival Required
Cell Time Time Fanout
Type (ns) (ns) Count Pin-Name
.........................................................
DFF 26.67 20.00 25 /vgacore-Optimized/hc
DFF 26.17 19.50 1 /vgacore-Optimized/hc
EQN 23.12 16.45 1 /vgacore-Optimized/C1
EQN 21.82 15.15 9 /vgacore-Optimized/C1
EQN 14.41 7.74 9 /vgacore-Optimized/C2
EQN 13.11 6.44 1 /vgacore-Optimized/C2
EQN 10.06 3.39 1 /vgacore-Optimized/C2
EQN 8.76 2.09 7 /vgacore-Optimized/C2
DFF 1.90 n/a 7 /vgacore-Optimized/hc
DFF 0.00 n/a 25 /vgacore-Optimized/hc
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