vgacore.out

来自「vga视频输出（vhdl）」· OUT 代码 · 共 107 行

Inferred memory devices in process 
	in routine vgacore line 29 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|         hcnt_reg         | Flip-flop |   9   |  Y  | Y  | N  | N  | N  | N  |
===============================================================================

hcnt_reg (width 9)
------------------
    Async-reset: reset



Inferred memory devices in process 
	in routine vgacore line 45 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|         vcnt_reg         | Flip-flop |  10   |  Y  | Y  | N  | N  | N  | N  |
===============================================================================

vcnt_reg (width 10)
-------------------
    Async-reset: reset



Inferred memory devices in process 
	in routine vgacore line 61 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|        hsyncb_reg        | Flip-flop |   1   |  -  | N  | Y  | N  | N  | N  |
===============================================================================

hsyncb_reg
----------
    Async-set: reset



Inferred memory devices in process 
	in routine vgacore line 77 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|        vsyncb_reg        | Flip-flop |   1   |  -  | N  | Y  | N  | N  | N  |
===============================================================================

vsyncb_reg
----------
    Async-set: reset



Inferred memory devices in process 
	in routine vgacore line 96 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|        pblank_reg        | Flip-flop |   1   |  -  | Y  | N  | N  | N  | N  |
===============================================================================

pblank_reg
----------
    Async-reset: reset



Inferred memory devices in process 
	in routine vgacore line 117 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|        pixrg_reg         | Flip-flop |   8   |  Y  | Y  | N  | N  | N  | N  |
===============================================================================

pixrg_reg (width 8)
-------------------
    Async-reset: reset



Inferred memory devices in process 
	in routine vgacore line 141 in file
         'F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|         rgb_reg          | Flip-flop |   6   |  Y  | Y  | N  | N  | N  | N  |
===============================================================================

rgb_reg (width 6)
-----------------
    Async-reset: reset


Writing to hnl file 'F:\XESSCORP\ELASCOMP\XSBRDS\designs\VGAVHDL\express/workdirs/WORK/vgacore.hnl'