📄 220model.vhd
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--------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be freely
-- copied and/or distributed at no cost. Any persons using this file for
-- any purpose do so at their own risk, and are responsible for the results
-- of such use. Altera Corporation does not guarantee that this file is
-- complete, correct, or fit for any particular purpose. NO WARRANTY OF
-- ANY KIND IS EXPRESSED OR IMPLIED. This notice must accompany any copy
-- of this file.
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
--------------------------------------------------------------------------
-- Version 1.7 (lpm 220) Date 07/13/99
--
-- 1. Changed LPM_RAM_IO so that it can be used to simulate both
-- MP2/Quartus behaviour and LPM220-compliant behaviour.
--
--------------------------------------------------------------------------
-- Version 1.6 (lpm 220) Date 06/15/99
--
-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
-- comply with the specfication.
-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
-- LPM_FIFO_DC; they are all initialized to 0's.
--------------------------------------------------------------------------
-- Version 1.5 (lpm 220) Date 05/10/99
--
-- Changed LPM_MODULUS from string type to integer.
--------------------------------------------------------------------------
-- Version 1.4 (lpm 220) Date 02/05/99
--
-- 1. Added LPM_DIVIDE module.
-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
-- and LPM_COMPARE
-- 3. Replaced the constants holding string with the actual string.
--------------------------------------------------------------------------
-- Version 1.3 Date 07/30/96
--
-- Modification History
--
-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
-- and LPM_PVALUE
--
-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
--------------------------------------------------------------------------
-- Excluded Functions:
--
-- LPM_FSM and LPM_TTABLE
--
--------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,
-- LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is
-- string "UNUSED".
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_CONSTANT is
generic (LPM_WIDTH : positive;
LPM_CVALUE : natural;
LPM_STRENGTH : string := "UNUSED";
LPM_TYPE : string := "LPM_CONSTANT";
LPM_HINT : string := "UNUSED");
port (RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_CONSTANT;
architecture LPM_SYN of LPM_CONSTANT is
begin
RESULT <= conv_std_logic_vector(LPM_CVALUE, LPM_WIDTH);
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_INV is
generic (LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_INV";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_INV;
architecture LPM_SYN of LPM_INV is
begin
RESULT <= not DATA;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_AND is
generic (LPM_WIDTH : positive;
LPM_SIZE : positive;
LPM_TYPE : string := "LPM_AND";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_AND;
architecture LPM_SYN of LPM_AND is
signal RESULT_INT : std_logic_2d(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);
begin
L1: for i in 0 to LPM_WIDTH-1 generate
RESULT_INT(0,i) <= DATA(0,i);
L2: for j in 0 to LPM_SIZE-2 generate
RESULT_INT(j+1,i) <= RESULT_INT(j,i) and DATA(j+1,i);
L3: if j = LPM_SIZE-2 generate
RESULT(i) <= RESULT_INT(LPM_SIZE-1,i);
end generate L3;
end generate L2;
end generate L1;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_OR is
generic (LPM_WIDTH : positive;
LPM_SIZE : positive;
LPM_TYPE : string := "LPM_OR";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_OR;
architecture LPM_SYN of LPM_OR is
signal RESULT_INT : std_logic_2d(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);
begin
L1: for i in 0 to LPM_WIDTH-1 generate
RESULT_INT(0,i) <= DATA(0,i);
L2: for j in 0 to LPM_SIZE-2 generate
RESULT_INT(j+1,i) <= RESULT_INT(j,i) or DATA(j+1,i);
L3: if j = LPM_SIZE-2 generate
RESULT(i) <= RESULT_INT(LPM_SIZE-1,i);
end generate L3;
end generate L2;
end generate L1;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_XOR is
generic (LPM_WIDTH : positive;
LPM_SIZE : positive;
LPM_TYPE : string := "LPM_XOR";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_XOR;
architecture LPM_SYN of LPM_XOR is
signal RESULT_INT : std_logic_2d(LPM_SIZE-1 downto 0,LPM_WIDTH-1 downto 0);
begin
L1: for i in 0 to LPM_WIDTH-1 generate
RESULT_INT(0,i) <= DATA(0,i);
L2: for j in 0 to LPM_SIZE-2 generate
RESULT_INT(j+1,i) <= RESULT_INT(j,i) xor DATA(j+1,i);
L3: if j = LPM_SIZE-2 generate
RESULT(i) <= RESULT_INT(LPM_SIZE-1,i);
end generate L3;
end generate L2;
end generate L1;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_BUSTRI is
generic (LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_BUSTRI";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ENABLEDT : in std_logic := '0';
ENABLETR : in std_logic := '0';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
TRIDATA : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_BUSTRI;
architecture LPM_SYN of LPM_BUSTRI is
begin
process(DATA, TRIDATA, ENABLETR, ENABLEDT)
begin
if ENABLEDT = '0' and ENABLETR = '1' then
RESULT <= TRIDATA;
TRIDATA <= (OTHERS => 'Z');
elsif ENABLEDT = '1' and ENABLETR = '0' then
RESULT <= (OTHERS => 'Z');
TRIDATA <= DATA;
elsif ENABLEDT = '1' and ENABLETR = '1' then
RESULT <= DATA;
TRIDATA <= DATA;
else
RESULT <= (OTHERS => 'Z');
TRIDATA <= (OTHERS => 'Z');
end if;
end process;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_MUX is
generic (LPM_WIDTH : positive;
LPM_SIZE : positive;
LPM_WIDTHS : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_MUX";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SEL : in std_logic_vector(LPM_WIDTHS-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_MUX;
architecture LPM_SYN of LPM_MUX is
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH-1 downto 0);
begin
process (ACLR, CLOCK, SEL, DATA)
variable resulttmp : t_resulttmp;
variable ISEL : integer;
begin
if LPM_PIPELINE >= 0 then
ISEL := conv_integer(SEL);
for i in 0 to LPM_WIDTH-1 loop
resulttmp(LPM_PIPELINE)(i) := DATA(ISEL,i);
end loop;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
RESULT <= resulttmp(0);
end if;
end process;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_DECODE is
generic (LPM_WIDTH : positive;
LPM_DECODES : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_DECODE";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
ACLR : in std_logic := '0';
ENABLE : in std_logic := '1';
EQ : out std_logic_vector(LPM_DECODES-1 downto 0));
end LPM_DECODE;
architecture LPM_SYN of LPM_DECODE is
type t_eqtmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_DECODES-1 downto 0);
begin
process(ACLR, CLOCK, DATA, ENABLE)
variable eqtmp : t_eqtmp;
begin
if LPM_PIPELINE >= 0 then
for i in 0 to LPM_DECODES-1 loop
if conv_integer(DATA) = i then
if ENABLE = '1' then
eqtmp(LPM_PIPELINE)(i) := '1';
else
eqtmp(LPM_PIPELINE)(i) := '0';
end if;
else
eqtmp(LPM_PIPELINE)(i) := '0';
end if;
end loop;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
eqtmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
eqtmp(0 to LPM_PIPELINE - 1) := eqtmp(1 to LPM_PIPELINE);
end if;
end if;
end if;
EQ <= eqtmp(0);
end process;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_CLSHIFT is
generic (LPM_WIDTH : positive;
LPM_WIDTHDIST : positive;
LPM_SHIFTTYPE : string := "LOGICAL";
LPM_TYPE : string := "LPM_CLSHIFT";
LPM_HINT : string := "UNUSED");
port (DATA : in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
DISTANCE : in STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 downto 0);
DIRECTION : in STD_LOGIC := '0';
RESULT : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
UNDERFLOW : out STD_LOGIC;
OVERFLOW : out STD_LOGIC);
end LPM_CLSHIFT;
architecture LPM_SYN of LPM_CLSHIFT is
signal IRESULT : std_logic_vector(LPM_WIDTH-1 downto 0);
signal TMPDATA : std_logic_vector(LPM_WIDTHDIST downto 1);
begin
process(DATA, DISTANCE, DIRECTION)
begin
TMPDATA <= (OTHERS => '0');
if LPM_SHIFTTYPE = "ARITHMETIC" then
if DIRECTION = '0' then
IRESULT <= conv_std_logic_vector((conv_integer(DATA) * (2**LPM_WIDTHDIST)), LPM_WIDTH);
else
IRESULT <= conv_std_logic_vector((conv_integer(DATA) / (2**LPM_WIDTHDIST)), LPM_WIDTH);
end if;
elsif LPM_SHIFTTYPE = "ROTATE" then
if DIRECTION = '0' then
IRESULT <= (DATA(LPM_WIDTH-LPM_WIDTHDIST-1 downto 0) &
DATA(LPM_WIDTH-1 downto LPM_WIDTH-LPM_WIDTHDIST));
else
IRESULT <= (DATA(LPM_WIDTHDIST-1 downto 0) &
DATA(LPM_WIDTH-1 downto LPM_WIDTHDIST));
end if;
else
if DIRECTION = '1' then
IRESULT <= (DATA(LPM_WIDTH-LPM_WIDTHDIST-1 downto 0) & TMPDATA);
else
IRESULT(LPM_WIDTH-LPM_WIDTHDIST-1 downto 0) <= DATA(LPM_WIDTH-1 downto LPM_WIDTHDIST);
IRESULT(LPM_WIDTH-1 downto LPM_WIDTH-LPM_WIDTHDIST) <= (OTHERS => '0');
end if;
end if;
end process;
process(IRESULT)
begin
if LPM_SHIFTTYPE = "LOGICAL" or LPM_SHIFTTYPE = "ROTATE" then
if IRESULT > 2 ** (LPM_WIDTH) then
OVERFLOW <= '1';
else
OVERFLOW <= '0';
end if;
if IRESULT = 0 then
UNDERFLOW <= '1';
else
UNDERFLOW <= '0';
end if;
else
OVERFLOW <= '0';
UNDERFLOW <= '0';
end if;
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