my_ram.edn

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2002 6 4 13 27 45)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 4.1i; Cores Update # 1 "))))
   (comment "This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of design files
limited to Xilinx devices or technologies. Use with non-Xilinx devices or
technologies is expressly prohibited and immediately terminates your license.
Xilinx products are not intended for use in life support appliances, devices,
or systems. Use in such applications are expressly prohibited.
Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.")
   (comment "Core parameters: ")
       (comment "c_sinit_value = 0 ")
       (comment "c_has_en = 0 ")
       (comment "c_reg_inputs = 1 ")
       (comment "c_yclk_is_rising = 1 ")
       (comment "c_ysinit_is_high = 1 ")
       (comment "c_ywe_is_high = 1 ")
       (comment "c_yprimitive_type = 4kx1 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_has_rdy = 1 ")
       (comment "c_write_mode = 0 ")
       (comment "c_width = 16 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_nd = 1 ")
       (comment "c_has_we = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_has_rfd = 1 ")
       (comment "c_has_din = 1 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_yen_is_high = 1 ")
       (comment "c_family = virtex ")
       (comment "InstanceName = my_ram ")
       (comment "c_depth = 256 ")
       (comment "c_has_default_data = 1 ")
       (comment "c_limit_data_pitch = 8 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_mem_init_file = mif_file_16_1 ")
       (comment "c_default_data = 0 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_addr_width = 8 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell RAMB4_S16 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WE (direction INPUT))
                   (port EN (direction INPUT))
                   (port RST (direction INPUT))
                   (port CLK (direction INPUT))
                   (port (rename DI_0_ "DI<0>") (direction INPUT))
                   (port (rename DI_1_ "DI<1>") (direction INPUT))
                   (port (rename DI_2_ "DI<2>") (direction INPUT))
                   (port (rename DI_3_ "DI<3>") (direction INPUT))
                   (port (rename DI_4_ "DI<4>") (direction INPUT))
                   (port (rename DI_5_ "DI<5>") (direction INPUT))
                   (port (rename DI_6_ "DI<6>") (direction INPUT))
                   (port (rename DI_7_ "DI<7>") (direction INPUT))
                   (port (rename DI_8_ "DI<8>") (direction INPUT))
                   (port (rename DI_9_ "DI<9>") (direction INPUT))
                   (port (rename DI_10_ "DI<10>") (direction INPUT))
                   (port (rename DI_11_ "DI<11>") (direction INPUT))
                   (port (rename DI_12_ "DI<12>") (direction INPUT))
                   (port (rename DI_13_ "DI<13>") (direction INPUT))
                   (port (rename DI_14_ "DI<14>") (direction INPUT))
                   (port (rename DI_15_ "DI<15>") (direction INPUT))
                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))
                   (port (rename DO_1_ "DO<1>") (direction OUTPUT))
                   (port (rename DO_2_ "DO<2>") (direction OUTPUT))
                   (port (rename DO_3_ "DO<3>") (direction OUTPUT))
                   (port (rename DO_4_ "DO<4>") (direction OUTPUT))
                   (port (rename DO_5_ "DO<5>") (direction OUTPUT))
                   (port (rename DO_6_ "DO<6>") (direction OUTPUT))
                   (port (rename DO_7_ "DO<7>") (direction OUTPUT))
                   (port (rename DO_8_ "DO<8>") (direction OUTPUT))
                   (port (rename DO_9_ "DO<9>") (direction OUTPUT))
                   (port (rename DO_10_ "DO<10>") (direction OUTPUT))
                   (port (rename DO_11_ "DO<11>") (direction OUTPUT))
                   (port (rename DO_12_ "DO<12>") (direction OUTPUT))
                   (port (rename DO_13_ "DO<13>") (direction OUTPUT))
                   (port (rename DO_14_ "DO<14>") (direction OUTPUT))
                   (port (rename DO_15_ "DO<15>") (direction OUTPUT))
                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))
                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))
                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))
                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))
                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))
                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))
                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))
                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell my_ram
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename addr_7_ "addr(7)") (direction INPUT))
   (port ( rename addr_6_ "addr(6)") (direction INPUT))
   (port ( rename addr_5_ "addr(5)") (direction INPUT))
   (port ( rename addr_4_ "addr(4)") (direction INPUT))
   (port ( rename addr_3_ "addr(3)") (direction INPUT))
   (port ( rename addr_2_ "addr(2)") (direction INPUT))
   (port ( rename addr_1_ "addr(1)") (direction INPUT))
   (port ( rename addr_0_ "addr(0)") (direction INPUT))
   (port ( rename clk "clk") (direction INPUT))
   (port ( rename din_15_ "din(15)") (direction INPUT))
   (port ( rename din_14_ "din(14)") (direction INPUT))
   (port ( rename din_13_ "din(13)") (direction INPUT))
   (port ( rename din_12_ "din(12)") (direction INPUT))
   (port ( rename din_11_ "din(11)") (direction INPUT))
   (port ( rename din_10_ "din(10)") (direction INPUT))
   (port ( rename din_9_ "din(9)") (direction INPUT))
   (port ( rename din_8_ "din(8)") (direction INPUT))
   (port ( rename din_7_ "din(7)") (direction INPUT))
   (port ( rename din_6_ "din(6)") (direction INPUT))
   (port ( rename din_5_ "din(5)") (direction INPUT))
   (port ( rename din_4_ "din(4)") (direction INPUT))
   (port ( rename din_3_ "din(3)") (direction INPUT))
   (port ( rename din_2_ "din(2)") (direction INPUT))
   (port ( rename din_1_ "din(1)") (direction INPUT))
   (port ( rename din_0_ "din(0)") (direction INPUT))
   (port ( rename nd "nd") (direction INPUT))
   (port ( rename we "we") (direction INPUT))
   (port ( rename dout_15_ "dout(15)") (direction OUTPUT))
   (port ( rename dout_14_ "dout(14)") (direction OUTPUT))
   (port ( rename dout_13_ "dout(13)") (direction OUTPUT))
   (port ( rename dout_12_ "dout(12)") (direction OUTPUT))
   (port ( rename dout_11_ "dout(11)") (direction OUTPUT))
   (port ( rename dout_10_ "dout(10)") (direction OUTPUT))
   (port ( rename dout_9_ "dout(9)") (direction OUTPUT))
   (port ( rename dout_8_ "dout(8)") (direction OUTPUT))
   (port ( rename dout_7_ "dout(7)") (direction OUTPUT))
   (port ( rename dout_6_ "dout(6)") (direction OUTPUT))
   (port ( rename dout_5_ "dout(5)") (direction OUTPUT))
   (port ( rename dout_4_ "dout(4)") (direction OUTPUT))
   (port ( rename dout_3_ "dout(3)") (direction OUTPUT))
   (port ( rename dout_2_ "dout(2)") (direction OUTPUT))
   (port ( rename dout_1_ "dout(1)") (direction OUTPUT))
   (port ( rename dout_0_ "dout(0)") (direction OUTPUT))
   (port ( rename rfd "rfd") (direction OUTPUT))
   (port ( rename rdy "rdy") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU0
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "dddd"))
   )
   (instance BU1
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU2
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU3
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU4
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU5
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU6
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU7
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU8
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU9
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU10
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU11
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU12
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU13
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU14
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU15
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU16
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU17
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU18
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU19
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU20
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU21
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU22
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU23
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU24
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU25
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU26
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU27
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance B69
      (viewRef view_1 (cellRef RAMB4_S16 (libraryRef xilinxun)))
      (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef I2 (instanceRef BU0))
      (portRef I3 (instanceRef BU0))
      (portRef RST (instanceRef B69))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef CE (instanceRef BU1))
      (portRef CE (instanceRef BU2))
      (portRef CE (instanceRef BU3))
      (portRef CE (instanceRef BU4))
      (portRef CE (instanceRef BU5))
      (portRef CE (instanceRef BU6))
      (portRef CE (instanceRef BU7))
      (portRef CE (instanceRef BU8))
      (portRef CE (instanceRef BU9))
      (portRef CE (instanceRef BU10))
      (portRef CE (instanceRef BU11))
      (portRef CE (instanceRef BU12))
      (portRef CE (instanceRef BU13))
      (portRef CE (instanceRef BU14))
      (portRef CE (instanceRef BU15))
      (portRef CE (instanceRef BU16))
      (portRef CE (instanceRef BU17))
      (portRef CE (instanceRef BU18))
      (portRef CE (instanceRef BU19))
      (portRef CE (instanceRef BU20))
      (portRef CE (instanceRef BU21))
      (portRef CE (instanceRef BU22))
      (portRef CE (instanceRef BU23))
      (portRef CE (instanceRef BU24))
      (portRef CE (instanceRef BU25))
      (portRef CE (instanceRef BU26))
      (portRef CE (instanceRef BU27))
      (portRef EN (instanceRef B69))
    )
   )
   (net N32
    (joined
      (portRef Q (instanceRef BU16))
      (portRef DI_15_ (instanceRef B69))
    )
   )
   (net N33
    (joined
      (portRef Q (instanceRef BU15))
      (portRef DI_14_ (instanceRef B69))
    )
   )
   (net N34
    (joined
      (portRef Q (instanceRef BU14))
      (portRef DI_13_ (instanceRef B69))
    )
   )
   (net N35
    (joined
      (portRef Q (instanceRef BU13))
      (portRef DI_12_ (instanceRef B69))
    )
   )
   (net N36
    (joined
      (portRef Q (instanceRef BU12))
      (portRef DI_11_ (instanceRef B69))
    )
   )
   (net N37
    (joined
      (portRef Q (instanceRef BU11))
      (portRef DI_10_ (instanceRef B69))
    )
   )
   (net N38
    (joined
      (portRef Q (instanceRef BU10))
      (portRef DI_9_ (instanceRef B69))
    )
   )
   (net N39
    (joined
      (portRef Q (instanceRef BU9))
      (portRef DI_8_ (instanceRef B69))
    )
   )
   (net N40
    (joined
      (portRef Q (instanceRef BU8))
      (portRef DI_7_ (instanceRef B69))
    )
   )
   (net N41
    (joined
      (portRef Q (instanceRef BU7))
      (portRef DI_6_ (instanceRef B69))
    )
   )
   (net N42
    (joined
      (portRef Q (instanceRef BU6))
      (portRef DI_5_ (instanceRef B69))
    )