sv_chip1.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

	v_corr_20_11: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_12: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_13: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_14: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_15: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_16: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_17: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_18: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_19: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_20: in std_logic_vector(corr_res_w-1 downto 0);
	bus_word_1: out std_logic_vector(7 downto 0);
	bus_word_2: out std_logic_vector(7 downto 0);
	bus_word_3: out std_logic_vector(7 downto 0);
	bus_word_4: out std_logic_vector(7 downto 0);
	bus_word_5: out std_logic_vector(7 downto 0);
	bus_word_6: out std_logic_vector(7 downto 0);
	counter_out: out std_logic_vector(2 downto 0));
end component;

begin
	port_bus_2to1_1_inst: port_bus_2to1_1 port map(
		tm3_clk_v0,
		vidin_addr_reg_2to3,
		svid_comp_switch_2to3, 
		vidin_new_data_scld_1_2to3_left,
		vidin_data_reg_scld_1_2to3_left_rp,
		vidin_data_reg_scld_1_2to3_left_ip,
		vidin_data_reg_scld_1_2to3_left_rn,
		vidin_data_reg_scld_1_2to3_left_in,
		vidin_new_data_scld_2_2to3_left,
		vidin_data_reg_scld_2_2to3_left_rp,
		vidin_data_reg_scld_2_2to3_left_ip,
		vidin_data_reg_scld_2_2to3_left_rn,
		vidin_data_reg_scld_2_2to3_left_in,
		vidin_new_data_scld_4_2to3_left,
		vidin_data_reg_scld_4_2to3_left_rp,
		vidin_data_reg_scld_4_2to3_left_ip,
		vidin_data_reg_scld_4_2to3_left_rn,
		vidin_data_reg_scld_4_2to3_left_in,
		vidin_new_data_scld_1_2to3_right,
		vidin_data_reg_scld_1_2to3_right_rp,
		vidin_data_reg_scld_1_2to3_right_ip,
		vidin_data_reg_scld_1_2to3_right_rn,
		vidin_data_reg_scld_1_2to3_right_in,
		vidin_new_data_scld_2_2to3_right,
		vidin_data_reg_scld_2_2to3_right_rp,
		vidin_data_reg_scld_2_2to3_right_ip,
		vidin_data_reg_scld_2_2to3_right_rn,
		vidin_data_reg_scld_2_2to3_right_in,
		vidin_new_data_scld_4_2to3_right,
		vidin_data_reg_scld_4_2to3_right_rp,
		vidin_data_reg_scld_4_2to3_right_ip,
		vidin_data_reg_scld_4_2to3_right_rn,
		vidin_data_reg_scld_4_2to3_right_in,
		bus_word_3_2to1,
		bus_word_4_2to1,
		bus_word_5_2to1,
		bus_word_6_2to1,
		counter_out_2to1);

wrapper_norm_corr_20_inst_p: wrapper_norm_corr_20 generic map(8)
		port map(
		tm3_clk_v0,
		vidin_new_data_scld_1_2to3_left,
		vidin_data_reg_scld_1_2to3_right_rp, -- changed in may 21, 2002
		vidin_data_reg_scld_1_2to3_right_ip, -- .......................
		vidin_data_reg_scld_1_2to3_left_rp, -- .......................
		vidin_data_reg_scld_1_2to3_left_ip, -- .......................
		corr_out_1_p(0),
		corr_out_1_p(1),
		corr_out_1_p(2),
		corr_out_1_p(3),
		corr_out_1_p(4),
		corr_out_1_p(5),
		corr_out_1_p(6),
		corr_out_1_p(7),
		corr_out_1_p(8),
		corr_out_1_p(9),
		corr_out_1_p(10),
		corr_out_1_p(11),
		corr_out_1_p(12),
		corr_out_1_p(13),
		corr_out_1_p(14),
		corr_out_1_p(15),
		corr_out_1_p(16),
		corr_out_1_p(17),
		corr_out_1_p(18),
		corr_out_1_p(19),
		corr_out_1_p(20));

wrapper_norm_corr_20_inst_n: wrapper_norm_corr_20 generic map(8)
		port map(
		tm3_clk_v0,
		vidin_new_data_scld_1_2to3_left,
		vidin_data_reg_scld_1_2to3_right_rn, -- changed in may 21, 2002
		vidin_data_reg_scld_1_2to3_right_in, -- .......................
		vidin_data_reg_scld_1_2to3_left_rn, -- .......................
		vidin_data_reg_scld_1_2to3_left_in, -- .......................
		corr_out_1_n(0),
		corr_out_1_n(1),
		corr_out_1_n(2),
		corr_out_1_n(3),
		corr_out_1_n(4),
		corr_out_1_n(5),
		corr_out_1_n(6),
		corr_out_1_n(7),
		corr_out_1_n(8),
		corr_out_1_n(9),
		corr_out_1_n(10),
		corr_out_1_n(11),
		corr_out_1_n(12),
		corr_out_1_n(13),
		corr_out_1_n(14),
		corr_out_1_n(15),
		corr_out_1_n(16),
		corr_out_1_n(17),
		corr_out_1_n(18),
		corr_out_1_n(19),
  	corr_out_1_n(20));


	wrapper_norm_corr_10_inst_p: wrapper_norm_corr_10 generic map(8)
		port map(
		tm3_clk_v0,
		vidin_new_data_scld_2_2to3_left,
		vidin_data_reg_scld_2_2to3_right_rp, -- changed in may 21, 2002
		vidin_data_reg_scld_2_2to3_right_ip, -- .......................
		vidin_data_reg_scld_2_2to3_left_rp, -- .......................
		vidin_data_reg_scld_2_2to3_left_ip, -- .......................
		corr_out_2_p(0),
		corr_out_2_p(1),
		corr_out_2_p(2),
		corr_out_2_p(3),
		corr_out_2_p(4),
		corr_out_2_p(5),
		corr_out_2_p(6),
		corr_out_2_p(7),
		corr_out_2_p(8),
		corr_out_2_p(9),
		corr_out_2_p(10));

	wrapper_norm_corr_10_inst_n: wrapper_norm_corr_10 generic map(8)
		port map(
		tm3_clk_v0,
		vidin_new_data_scld_2_2to3_left,
		vidin_data_reg_scld_2_2to3_right_rn, -- changed in may 21, 2002
		vidin_data_reg_scld_2_2to3_right_in, -- .......................
		vidin_data_reg_scld_2_2to3_left_rn, -- .......................
		vidin_data_reg_scld_2_2to3_left_in, -- .......................
		corr_out_2_n(0),
		corr_out_2_n(1),
		corr_out_2_n(2),
		corr_out_2_n(3),
		corr_out_2_n(4),
		corr_out_2_n(5),
		corr_out_2_n(6),
		corr_out_2_n(7),
		corr_out_2_n(8),
		corr_out_2_n(9),
		corr_out_2_n(10));
	

	wrapper_norm_corr_5_inst_p: wrapper_norm_corr_5_seq generic map(8)
		port map(
		tm3_clk_v0,
		vidin_new_data_scld_4_2to3_left,
		vidin_data_reg_scld_4_2to3_right_rp, -- changed in may 21, 2002
		vidin_data_reg_scld_4_2to3_right_ip, -- .......................
		vidin_data_reg_scld_4_2to3_left_rp, -- .......................
		vidin_data_reg_scld_4_2to3_left_ip, -- .......................
		corr_out_4_p(0),
		corr_out_4_p(1),
		corr_out_4_p(2),
		corr_out_4_p(3),
		corr_out_4_p(4),
		corr_out_4_p(5));

	wrapper_norm_corr_5_inst_n: wrapper_norm_corr_5_seq generic map(8)
		port map(
		tm3_clk_v0,
		vidin_new_data_scld_4_2to3_left,
		vidin_data_reg_scld_4_2to3_right_rn, -- changed in may 21, 2002
		vidin_data_reg_scld_4_2to3_right_in, -- .......................
		vidin_data_reg_scld_4_2to3_left_rn, -- .......................
		vidin_data_reg_scld_4_2to3_left_in, -- .......................
		corr_out_4_n(0),
		corr_out_4_n(1),
		corr_out_4_n(2),
		corr_out_4_n(3),
		corr_out_4_n(4),
		corr_out_4_n(5));


port_bus_1to0_inst: port_bus_1to0 generic map(8)
		port map(
			tm3_clk_v0,
			vidin_addr_reg_2to3,
			svid_comp_switch_2to3, 
			vidin_new_data_scld_1_2to3_left,
			corr_out_4(0)(17) & corr_out_4(0)(15 downto 9), --- scale 4  inputs
			corr_out_4(1)(17) & corr_out_4(1)(15 downto 9), --- scale 4  inputs
			corr_out_4(2)(17) & corr_out_4(2)(15 downto 9),
			corr_out_4(3)(17) & corr_out_4(3)(15 downto 9),
			corr_out_4(4)(17) & corr_out_4(4)(15 downto 9),
			corr_out_4(5)(17) & corr_out_4(5)(15 downto 9),
			corr_out_2(0)(17) & corr_out_2(0)(15 downto 9), --- scale 2  inputs
			corr_out_2(1)(17) & corr_out_2(1)(15 downto 9), --- scale 2  inputs
			corr_out_2(2)(17) & corr_out_2(2)(15 downto 9),
			corr_out_2(3)(17) & corr_out_2(3)(15 downto 9),
			corr_out_2(4)(17) & corr_out_2(4)(15 downto 9),
			corr_out_2(5)(17) & corr_out_2(5)(15 downto 9),
			corr_out_2(6)(17) & corr_out_2(6)(15 downto 9),
			corr_out_2(7)(17) & corr_out_2(7)(15 downto 9),
			corr_out_2(8)(17) & corr_out_2(8)(15 downto 9),
			corr_out_2(9)(17) & corr_out_2(9)(15 downto 9),
			corr_out_2(10)(17) & corr_out_2(10)(15 downto 9),
			corr_out_1(0)(17) & corr_out_1(0)(15 downto 9), -- scale 1 inputs
			corr_out_1(1)(17) & corr_out_1(1)(15 downto 9), -- scale 1 inputs
			corr_out_1(2)(17) & corr_out_1(2)(15 downto 9),
			corr_out_1(3)(17) & corr_out_1(3)(15 downto 9),
			corr_out_1(4)(17) & corr_out_1(4)(15 downto 9),
			corr_out_1(5)(17) & corr_out_1(5)(15 downto 9),
			corr_out_1(6)(17) & corr_out_1(6)(15 downto 9),
			corr_out_1(7)(17) & corr_out_1(7)(15 downto 9),
			corr_out_1(8)(17) & corr_out_1(8)(15 downto 9),
			corr_out_1(9)(17) & corr_out_1(9)(15 downto 9),
			corr_out_1(10)(17) & corr_out_1(10)(15 downto 9),
			corr_out_1(11)(17) & corr_out_1(11)(15 downto 9),
			corr_out_1(12)(17) & corr_out_1(12)(15 downto 9),
			corr_out_1(13)(17) & corr_out_1(13)(15 downto 9),
			corr_out_1(14)(17) & corr_out_1(14)(15 downto 9),
			corr_out_1(15)(17) & corr_out_1(15)(15 downto 9),
			corr_out_1(16)(17) & corr_out_1(16)(15 downto 9),
			corr_out_1(17)(17) & corr_out_1(17)(15 downto 9),
			corr_out_1(18)(17) & corr_out_1(18)(15 downto 9),
			corr_out_1(19)(17) & corr_out_1(19)(15 downto 9),
			corr_out_1(20)(17) & corr_out_1(20)(15 downto 9),
			bus_word_1_1to0,
			bus_word_2_1to0,
			bus_word_3_1to0,
			bus_word_4_1to0,
			bus_word_5_1to0,
			bus_word_6_1to0,
			counter_out_1to0);	


	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then		
			if vidin_new_data_scld_1_2to3_left = '1' then
				for i in 0 to 20 loop
					corr_out_1(i) <= 	(corr_out_1_p(i)(15) & corr_out_1_p(i)(15) & corr_out_1_p(i)) +  
								(corr_out_1_n(i)(15) & corr_out_1_n(i)(15) & corr_out_1_n(i)); -- +  
								--(corr_out_1_n(i)(15) & corr_out_1_n(i)(15) & corr_out_1_n(i));
				end loop;
			end if;
		end if;
	end process;

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then		
			if vidin_new_data_scld_2_2to3_left = '1' then
				for i in 0 to 10 loop
					corr_out_2(i) <= 	(corr_out_2_p(i)(15) & corr_out_2_p(i)(15) & corr_out_2_p(i)) +  
								(corr_out_2_n(i)(15) & corr_out_2_n(i)(15) & corr_out_2_n(i)); -- +  
								--(corr_out_2_n(i)(15) & corr_out_2_n(i)(15) & corr_out_2_n(i));
				end loop;
			end if;
		end if;
	end process;

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then		
			if vidin_new_data_scld_2_2to3_left = '1' then
				for i in 0 to 5 loop
					corr_out_4(i) <= 	(corr_out_4_p(i)(15) & corr_out_4_p(i)(15) & corr_out_4_p(i)) +  
								(corr_out_4_n(i)(15) & corr_out_4_n(i)(15) & corr_out_4_n(i)); -- +  
								--(corr_out_4_n(i)(15) & corr_out_4_n(i)(15) & corr_out_4_n(i));
				end loop;
			end if;
		end if;
	end process;


  
	process(tm3_clk_v0) begin