sv_chip1.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

-- created by Ahmad darabiha
-- last updated Aug. 2002
-- this is the design for chip #1 of stereo 
-- vision system. this chip mainly performs the 
-- normalization and correlation in two orienations
-- and 3 scales.
 
library ieee;
use work.basic_type.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sv_chip1 is port(
	tm3_clk_v0: in std_logic;
	tm3_sram_data : inout std_logic_vector(63 downto 0);
	tm3_sram_addr : out std_logic_vector(18 downto 0);
	tm3_sram_we : out std_logic_vector(7 downto 0);
	tm3_sram_oe : out std_logic_vector(1 downto 0);
	tm3_sram_adsp : out std_logic;
	bus_word_3_2to1: in std_logic_vector(15 downto 0);
	bus_word_4_2to1: in std_logic_vector(15 downto 0);
	bus_word_5_2to1: in std_logic_vector(15 downto 0);
	bus_word_6_2to1: in std_logic_vector(15 downto 0);
	counter_out_2to1: in std_logic_vector(2 downto 0);
	bus_word_1_1to0: out std_logic_vector(7 downto 0);
	bus_word_2_1to0: out std_logic_vector(7 downto 0);
	bus_word_3_1to0: out std_logic_vector(7 downto 0);
	bus_word_4_1to0: out std_logic_vector(7 downto 0);
	bus_word_5_1to0: out std_logic_vector(7 downto 0);
	bus_word_6_1to0: out std_logic_vector(7 downto 0);
	counter_out_1to0: out std_logic_vector(2 downto 0));
end sv_chip1;

architecture arch_sv_chip1 of sv_chip1 is
	signal horiz: std_logic_vector(9 downto 0);
	signal vert: std_logic_vector(9 downto 0);
	signal vidin_data_buf_sc_1 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_1 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_1 : std_logic_vector(18 downto 0);
	signal vidin_data_buf_sc_2 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_2 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_2 : std_logic_vector(18 downto 0);
	signal vidin_data_buf_sc_4 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_4 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_4 : std_logic_vector(18 downto 0);
	signal video_state : std_logic;
	
	signal vidin_new_data_scld_1_2to3_left_reg: std_logic;
	signal vidin_data_reg_scld_1_2to3_left_reg:  std_logic_vector(7 downto 0);
	--signal vidin_data_reg_scld_1_2to3_left_iz_reg:  std_logic_vector(7 downto 0);
	
	signal vidin_new_data_scld_2_2to3_left_reg: std_logic;
	signal vidin_data_reg_scld_2_2to3_left_reg:  std_logic_vector(7 downto 0);
	--signal vidin_data_reg_scld_2_2to3_left_iz_reg:  std_logic_vector(7 downto 0);
	
	signal vidin_new_data_scld_4_2to3_left_reg: std_logic;
	signal vidin_data_reg_scld_4_2to3_left_reg:  std_logic_vector(7 downto 0);
	--signal vidin_data_reg_scld_4_2to3_left_iz_reg:  std_logic_vector(7 downto 0);
	
	signal vidin_new_data_scld_1_2to3_right_reg: std_logic;
	signal vidin_data_reg_scld_1_2to3_right_reg:  std_logic_vector(7 downto 0);
	--signal vidin_data_reg_scld_1_2to3_right_iz_reg:  std_logic_vector(7 downto 0);
	
	signal vidin_new_data_scld_2_2to3_right_reg: std_logic;
	signal vidin_data_reg_scld_2_2to3_right_reg:  std_logic_vector(7 downto 0);
	--signal vidin_data_reg_scld_2_2to3_right_iz_reg:  std_logic_vector(7 downto 0);
	
	signal vidin_new_data_scld_4_2to3_right_reg: std_logic;
	signal vidin_data_reg_scld_4_2to3_right_reg:  std_logic_vector(7 downto 0);
	--signal vidin_data_reg_scld_4_2to3_right_iz_reg:  std_logic_vector(7 downto 0);
	
	signal vidin_addr_reg_2to3_reg: std_logic_vector(18 downto 0);
	
	signal vidin_new_data_scld_1_2to3_left: std_logic;
	signal vidin_data_reg_scld_1_2to3_left_rz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_left_iz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_left_rp: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_left_ip: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_left_rn: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_left_in: std_logic_vector(15 downto 0);
		
	signal vidin_new_data_scld_2_2to3_left: std_logic;
	signal vidin_data_reg_scld_2_2to3_left_rz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_left_iz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_left_rp: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_left_ip: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_left_rn: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_left_in: std_logic_vector(15 downto 0);
	
	signal vidin_new_data_scld_4_2to3_left: std_logic;
	signal vidin_data_reg_scld_4_2to3_left_rz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_left_iz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_left_rp: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_left_ip: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_left_rn: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_left_in: std_logic_vector(15 downto 0);
	
	signal vidin_new_data_scld_1_2to3_right: std_logic;
	signal vidin_data_reg_scld_1_2to3_right_rz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_right_iz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_right_rp: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_right_ip: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_right_rn: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_1_2to3_right_in: std_logic_vector(15 downto 0);
	
	signal vidin_new_data_scld_2_2to3_right: std_logic;
	signal vidin_data_reg_scld_2_2to3_right_rz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_right_iz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_right_rp: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_right_ip: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_right_rn: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_2_2to3_right_in: std_logic_vector(15 downto 0);
	
	signal vidin_new_data_scld_4_2to3_right: std_logic;
	signal vidin_data_reg_scld_4_2to3_right_rz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_right_iz: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_right_rp: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_right_ip: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_right_rn: std_logic_vector(15 downto 0);
	signal vidin_data_reg_scld_4_2to3_right_in: std_logic_vector(15 downto 0);
	
	
	signal vidin_addr_reg_2to3: std_logic_vector(18 downto 0);
	signal svid_comp_switch_2to3: std_logic;
	
	--signal corr_out_01_1_z,corr_out_02_1_z,corr_out_03_1_z,corr_out_04_1_z,
	--		corr_out_05_1_z,corr_out_06_1_z,corr_out_07_1_z,corr_out_08_1_z,
	--		corr_out_09_1_z,corr_out_10_1_z,corr_out_11_1_z,corr_out_12_1_z,
	--		corr_out_13_1_z,corr_out_14_1_z,corr_out_15_1_z,corr_out_16_1_z,
	--		corr_out_17_1_z,corr_out_18_1_z,corr_out_19_1_z,corr_out_20_1_z: std_logic_vector(15 downto 0);

	signal corr_out_1_z, corr_out_1_p, corr_out_1_n : type_array_16_20;
	signal corr_out_1 : type_array_18_20;

	signal corr_out_2_z, corr_out_2_p, corr_out_2_n : type_array_16_10;
	signal corr_out_2 : type_array_18_10;

	signal corr_out_4_z, corr_out_4_p, corr_out_4_n : type_array_16_5;
	signal corr_out_4 : type_array_18_5;


	component port_bus_2to1_1 port(
		clk: in std_logic;
		vidin_addr_reg: out std_logic_vector(18 downto 0);
		svid_comp_switch : out std_logic;
		vidin_new_data_scld_1_2to3_left: out std_logic;
		vidin_data_reg_scld_1_2to3_left_rp: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_left_ip: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_left_rn: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_left_in: out std_logic_vector(15 downto 0);
		vidin_new_data_scld_2_2to3_left: out std_logic;
		vidin_data_reg_scld_2_2to3_left_rp: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_ip: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_rn: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_in: out std_logic_vector(15 downto 0);
		vidin_new_data_scld_4_2to3_left: out std_logic;
		vidin_data_reg_scld_4_2to3_left_rp: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_ip: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_rn: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_in: out std_logic_vector(15 downto 0);
		vidin_new_data_scld_1_2to3_right: out std_logic;
		vidin_data_reg_scld_1_2to3_right_rp: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_ip: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_rn: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_in: out std_logic_vector(15 downto 0);
		vidin_new_data_scld_2_2to3_right: out std_logic;
		vidin_data_reg_scld_2_2to3_right_rp: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_ip: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_rn: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_in: out std_logic_vector(15 downto 0);
		vidin_new_data_scld_4_2to3_right: out std_logic;
		vidin_data_reg_scld_4_2to3_right_rp: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_ip: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_rn: out std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_in: out std_logic_vector(15 downto 0);
		bus_word_3: in std_logic_vector(15 downto 0);
		bus_word_4: in std_logic_vector(15 downto 0);
		bus_word_5: in std_logic_vector(15 downto 0);
		bus_word_6: in std_logic_vector(15 downto 0);
		counter_out: in std_logic_vector(2 downto 0));
	end component;
	
	component wrapper_norm_corr_20  generic(sh_reg_w :integer);
		port(
 	 	clk : in std_logic;
		wen : in std_logic;
		d_l_1 : in std_logic_vector(15 downto 0);
		d_l_2 : in std_logic_vector(15 downto 0);
		d_r_1: in std_logic_vector(15 downto 0);
		d_r_2: in std_logic_vector(15 downto 0);
		corr_out_0: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_1: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_2: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_3: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_4: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_5: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_6: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_7: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_8: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_9: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_10: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_11: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_12: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_13: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_14: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_15: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_16: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_17: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_18: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_19: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_20: out std_logic_vector(2*sh_reg_w-1 downto 0));
end component;

component wrapper_norm_corr_10  generic(sh_reg_w :integer);
		port(
 	 	clk : in std_logic;
		wen : in std_logic;
		d_l_1 : in std_logic_vector(15 downto 0);
		d_l_2 : in std_logic_vector(15 downto 0);
		d_r_1: in std_logic_vector(15 downto 0);
		d_r_2: in std_logic_vector(15 downto 0);
		corr_out_0: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_1: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_2: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_3: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_4: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_5: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_6: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_7: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_8: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_9: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_10: out std_logic_vector(2*sh_reg_w-1 downto 0));
end component;

component wrapper_norm_corr_5_seq  generic(sh_reg_w :integer);
		port(
 	 	clk : in std_logic;
		wen : in std_logic;
		d_l_1 : in std_logic_vector(15 downto 0);
		d_l_2 : in std_logic_vector(15 downto 0);
		d_r_1: in std_logic_vector(15 downto 0);
		d_r_2: in std_logic_vector(15 downto 0);
		corr_out_0: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_1: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_2: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_3: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_4: out std_logic_vector(2*sh_reg_w-1 downto 0);
		corr_out_5: out std_logic_vector(2*sh_reg_w-1 downto 0));
end component;

component port_bus_1to0 generic(corr_res_w: integer);
	port(
	clk: in std_logic;
	vidin_addr_reg: in std_logic_vector(18 downto 0);
	svid_comp_switch : in std_logic;
	vidin_new_data_scld_1_2to3_left: in std_logic;
	v_corr_05_00: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_05_01: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_05_02: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_05_03: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_05_04: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_05_05: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_00: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_01: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_02: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_03: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_04: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_05: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_06: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_07: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_08: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_09: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_10_10: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_00: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_01: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_02: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_03: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_04: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_05: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_06: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_07: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_08: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_09: in std_logic_vector(corr_res_w-1 downto 0);
	v_corr_20_10: in std_logic_vector(corr_res_w-1 downto 0);