my_fifo.edn

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2002 6 14 14 7 42)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 4.1i; Cores Update # 1 "))))
   (comment "This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of design files
limited to Xilinx devices or technologies. Use with non-Xilinx devices or
technologies is expressly prohibited and immediately terminates your license.
Xilinx products are not intended for use in life support appliances, devices,
or systems. Use in such applications are expressly prohibited.
Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.")
   (comment "Core parameters: ")
       (comment "c_has_aset = false ")
       (comment "c_read_mif = false ")
       (comment "c_has_a = false ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_sclr = false ")
       (comment "c_width = 8 ")
       (comment "c_enable_rlocs = true ")
       (comment "c_default_data_radix = 1 ")
       (comment "c_ainit_val = 00000000 ")
       (comment "c_generate_mif = true ")
       (comment "c_has_ce = true ")
       (comment "c_family = virtex ")
       (comment "c_has_aclr = false ")
       (comment "InstanceName = my_fifo ")
       (comment "c_sync_enable = 0 ")
       (comment "c_depth = 13 ")
       (comment "c_mem_init_radix = 1 ")
       (comment "c_has_ainit = false ")
       (comment "c_sinit_val = 00000000 ")
       (comment "c_has_sset = false ")
       (comment "c_has_sinit = false ")
       (comment "c_shift_type = 0 ")
       (comment "c_mem_init_file = my_fifo.mif ")
       (comment "c_default_data = 0 ")
       (comment "c_reg_last_bit = false ")
       (comment "c_addr_width = 4 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell SRL16E (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell my_fifo
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename CLK "CLK") (direction INPUT))
   (port ( rename D_0_ "D(0)") (direction INPUT))
   (port ( rename D_1_ "D(1)") (direction INPUT))
   (port ( rename D_2_ "D(2)") (direction INPUT))
   (port ( rename D_3_ "D(3)") (direction INPUT))
   (port ( rename D_4_ "D(4)") (direction INPUT))
   (port ( rename D_5_ "D(5)") (direction INPUT))
   (port ( rename D_6_ "D(6)") (direction INPUT))
   (port ( rename D_7_ "D(7)") (direction INPUT))
   (port ( rename CE "CE") (direction INPUT))
   (port ( rename Q_0_ "Q(0)") (direction OUTPUT))
   (port ( rename Q_1_ "Q(1)") (direction OUTPUT))
   (port ( rename Q_2_ "Q(2)") (direction OUTPUT))
   (port ( rename Q_3_ "Q(3)") (direction OUTPUT))
   (port ( rename Q_4_ "Q(4)") (direction OUTPUT))
   (port ( rename Q_5_ "Q(5)") (direction OUTPUT))
   (port ( rename Q_6_ "Q(6)") (direction OUTPUT))
   (port ( rename Q_7_ "Q(7)") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU0
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU1
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU2
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU3
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU4
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU5
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU6
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU7
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU8
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU9
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU10
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU11
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU12
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU13
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
   )
   (instance BU14
      (viewRef view_1 (cellRef SRL16E (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
      (property INIT (string "0000"))
   )
   (instance BU15
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef A2 (instanceRef BU0))
      (portRef A2 (instanceRef BU2))
      (portRef A2 (instanceRef BU4))
      (portRef A2 (instanceRef BU6))
      (portRef A2 (instanceRef BU8))
      (portRef A2 (instanceRef BU10))
      (portRef A2 (instanceRef BU12))
      (portRef A2 (instanceRef BU14))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef A0 (instanceRef BU0))
      (portRef A0 (instanceRef BU2))
      (portRef A0 (instanceRef BU4))
      (portRef A0 (instanceRef BU6))
      (portRef A0 (instanceRef BU8))
      (portRef A0 (instanceRef BU10))
      (portRef A0 (instanceRef BU12))
      (portRef A0 (instanceRef BU14))
      (portRef A1 (instanceRef BU0))
      (portRef A1 (instanceRef BU2))
      (portRef A1 (instanceRef BU4))
      (portRef A1 (instanceRef BU6))
      (portRef A1 (instanceRef BU8))
      (portRef A1 (instanceRef BU10))
      (portRef A1 (instanceRef BU12))
      (portRef A1 (instanceRef BU14))
      (portRef A3 (instanceRef BU0))
      (portRef A3 (instanceRef BU2))
      (portRef A3 (instanceRef BU4))
      (portRef A3 (instanceRef BU6))
      (portRef A3 (instanceRef BU8))
      (portRef A3 (instanceRef BU10))
      (portRef A3 (instanceRef BU12))
      (portRef A3 (instanceRef BU14))
    )
   )
   (net (rename N10 "CLK")
    (joined
      (portRef CLK)
      (portRef CLK (instanceRef BU0))
      (portRef CLK (instanceRef BU2))
      (portRef CLK (instanceRef BU4))
      (portRef CLK (instanceRef BU6))
      (portRef CLK (instanceRef BU8))
      (portRef CLK (instanceRef BU10))
      (portRef CLK (instanceRef BU12))
      (portRef CLK (instanceRef BU14))
      (portRef C (instanceRef BU1))
      (portRef C (instanceRef BU3))
      (portRef C (instanceRef BU5))
      (portRef C (instanceRef BU7))
      (portRef C (instanceRef BU9))
      (portRef C (instanceRef BU11))
      (portRef C (instanceRef BU13))
      (portRef C (instanceRef BU15))
    )
   )
   (net (rename N11 "D(0)")
    (joined
      (portRef D_0_)
      (portRef D (instanceRef BU0))
    )
   )
   (net (rename N12 "D(1)")
    (joined
      (portRef D_1_)
      (portRef D (instanceRef BU2))
    )
   )
   (net (rename N13 "D(2)")
    (joined
      (portRef D_2_)
      (portRef D (instanceRef BU4))
    )
   )
   (net (rename N14 "D(3)")
    (joined
      (portRef D_3_)
      (portRef D (instanceRef BU6))
    )
   )
   (net (rename N15 "D(4)")
    (joined
      (portRef D_4_)
      (portRef D (instanceRef BU8))
    )
   )
   (net (rename N16 "D(5)")
    (joined
      (portRef D_5_)
      (portRef D (instanceRef BU10))
    )
   )
   (net (rename N17 "D(6)")
    (joined
      (portRef D_6_)
      (portRef D (instanceRef BU12))
    )
   )
   (net (rename N18 "D(7)")
    (joined
      (portRef D_7_)
      (portRef D (instanceRef BU14))
    )
   )
   (net (rename N19 "Q(0)")
    (joined
      (portRef Q_0_)
      (portRef Q (instanceRef BU1))
    )
   )
   (net (rename N20 "Q(1)")
    (joined
      (portRef Q_1_)
      (portRef Q (instanceRef BU3))
    )
   )
   (net (rename N21 "Q(2)")
    (joined
      (portRef Q_2_)
      (portRef Q (instanceRef BU5))
    )
   )
   (net (rename N22 "Q(3)")
    (joined
      (portRef Q_3_)
      (portRef Q (instanceRef BU7))
    )
   )
   (net (rename N23 "Q(4)")
    (joined
      (portRef Q_4_)
      (portRef Q (instanceRef BU9))
    )
   )
   (net (rename N24 "Q(5)")
    (joined
      (portRef Q_5_)
      (portRef Q (instanceRef BU11))
    )
   )
   (net (rename N25 "Q(6)")
    (joined
      (portRef Q_6_)
      (portRef Q (instanceRef BU13))
    )
   )
   (net (rename N26 "Q(7)")
    (joined
      (portRef Q_7_)
      (portRef Q (instanceRef BU15))
    )
   )
   (net (rename N27 "CE")
    (joined
      (portRef CE)
      (portRef CE (instanceRef BU0))
      (portRef CE (instanceRef BU2))
      (portRef CE (instanceRef BU4))
      (portRef CE (instanceRef BU6))
      (portRef CE (instanceRef BU8))
      (portRef CE (instanceRef BU10))
      (portRef CE (instanceRef BU12))
      (portRef CE (instanceRef BU14))
      (portRef CE (instanceRef BU1))
      (portRef CE (instanceRef BU3))
      (portRef CE (instanceRef BU5))
      (portRef CE (instanceRef BU7))
      (portRef CE (instanceRef BU9))
      (portRef CE (instanceRef BU11))
      (portRef CE (instanceRef BU13))
      (portRef CE (instanceRef BU15))
    )
   )
   (net N40
    (joined
      (portRef Q (instanceRef BU0))
      (portRef D (instanceRef BU1))
    )
   )
   (net N41
    (joined
      (portRef Q (instanceRef BU2))
      (portRef D (instanceRef BU3))
    )
   )
   (net N42
    (joined
      (portRef Q (instanceRef BU4))
      (portRef D (instanceRef BU5))
    )
   )
   (net N43
    (joined
      (portRef Q (instanceRef BU6))
      (portRef D (instanceRef BU7))
    )
   )
   (net N44
    (joined
      (portRef Q (instanceRef BU8))
      (portRef D (instanceRef BU9))
    )
   )
   (net N45
    (joined
      (portRef Q (instanceRef BU10))
      (portRef D (instanceRef BU11))
    )
   )
   (net N46
    (joined
      (portRef Q (instanceRef BU12))
      (portRef D (instanceRef BU13))
    )
   )
   (net N47
    (joined
      (portRef Q (instanceRef BU14))
      (portRef D (instanceRef BU15))
    )
   )
))))
(design my_fifo (cellRef my_fifo (libraryRef test_lib))
  (property PART (string "XCV100BG256") (owner "Xilinx")))
)