sv_chip2.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

				vidin_v_out_4_h1_right,
				vidin_v_out_4_h2_right,
				vidin_v_out_4_h3_right,
				vidin_v_out_4_h4_right,
				open);							

	h_fltr_1_right: h_fltr port map(tm3_clk_v0,
				v_nd_s1_right,  	
				vidin_v_out_1_f1_right,
				vidin_v_out_1_f2_right,
				vidin_v_out_1_f3_right,
				vidin_v_out_1_h1_right,
				vidin_v_out_1_h2_right,
				vidin_v_out_1_h3_right,
				vidin_v_out_1_h4_right,
				real_z_1_right, 
				imag_z_1_right,
				real_p_1_right,
				imag_p_1_right,
                real_n_1_right,
				imag_n_1_right);


				
	h_fltr_2_right: h_fltr port map(tm3_clk_v0,
				v_nd_s2_right,  	
				vidin_v_out_2_f1_right,
				vidin_v_out_2_f2_right,
				vidin_v_out_2_f3_right,
				vidin_v_out_2_h1_right,
				vidin_v_out_2_h2_right,
				vidin_v_out_2_h3_right,
				vidin_v_out_2_h4_right,
				real_z_2_right, 
				imag_z_2_right,
				real_p_2_right,
				imag_p_2_right,
                real_n_2_right,
				imag_n_2_right);

				

	h_fltr_4_right: h_fltr port map(tm3_clk_v0,
				v_nd_s4_right,  	
				vidin_v_out_4_f1_right,
				vidin_v_out_4_f2_right,
				vidin_v_out_4_f3_right,
				vidin_v_out_4_h1_right,
				vidin_v_out_4_h2_right,
				vidin_v_out_4_h3_right,
				vidin_v_out_4_h4_right,
				real_z_4_right, 
				imag_z_4_right,
				real_p_4_right,
				imag_p_4_right,
                real_n_4_right,
				imag_n_4_right); 


-----------------------------------------------------------------------------------------------------
----------------------         sending filter results to bus_interface module   ---------------------
-----------------------------------------------------------------------------------------------------


	port_bus_2to1_inst: port_bus_2to1 port map(
		tm3_clk_v0,
		vidin_addr_reg_2to3,
		svid_comp_switch_2to3, 
		v_nd_s1_left,
		real_p_1_left,
		imag_p_1_left,
        real_n_1_left,
		imag_n_1_left,
		real_p_2_left,
		imag_p_2_left,
        real_n_2_left,
		imag_n_2_left,
		real_p_4_left,
		imag_p_4_left,
        real_n_4_left,
		imag_n_4_left, 
		real_p_1_right,
		imag_p_1_right,
        real_n_1_right,
		imag_n_1_right,
		real_p_2_right,
		imag_p_2_right,
        real_n_2_right,
		imag_n_2_right,
 		real_p_4_right,
		imag_p_4_right,
        real_n_4_right,
		imag_n_4_right, 
		bus_word_3_2to1,
		bus_word_4_2to1,
		bus_word_5_2to1,
		bus_word_6_2to1,
		counter_out_2to1);


-----------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------


	--tm3_vidout_clock <= not(video_state);

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then
			video_state <= not(video_state);
			if video_state = '0' then
				if horiz = 800 then
					horiz <= "0000000000";
					if vert = 525 then
						vert <= "0000000000";
					else
						vert <= vert + 1;
					end if;
				else
					horiz <= horiz + 1;
				end if;

				tm3_sram_adsp <= '1';
				tm3_sram_we <= "11111111";
				tm3_sram_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
				case horiz(2 downto 0) is 
			        when "000" => 
						tm3_sram_oe <= "10";
				
				when "001" => 
						tm3_sram_oe <= "11";
				
				when "010" => 
						tm3_sram_oe <= "10";
				
				when "011" => 
						tm3_sram_oe <= "11";
				
				when "100" => 
						tm3_sram_oe <= "11";
				
				when "101" => 
						tm3_sram_oe <= "11";
					
				when "110" => 
						tm3_sram_oe <= "11"; --"10";
				
				when "111" => 
						tm3_sram_oe <= "11";
				
			     end case;	
				
			else
				tm3_sram_adsp <= '0';
				
				case horiz(2 downto 0) is
				
					when "000" =>
						tm3_sram_addr <= "00000" & vidin_addr_buf_sc_1_fifo;					
			            tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
					
					when "001" =>
						vidout_buf_fifo_1_left <= tm3_sram_data;
						tm3_sram_addr <= vidin_addr_buf_sc_1;
						tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= vidin_data_buf_sc_1;
					
					when "010" =>
					    tm3_sram_addr <= "00001" & vidin_addr_buf_sc_1_fifo;					
			            tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
					
					      
					when "011" => 
						vidout_buf_fifo_1_right <= tm3_sram_data;
						tm3_sram_addr <= vidin_addr_buf_sc_1;
						tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= vidin_data_buf_sc_1;
					
					when "100" =>
						    tm3_sram_addr <= "00000" & vidin_addr_buf_sc_1_fifo;					
			                tm3_sram_we <= "11111111";
							tm3_sram_oe <= "11";
							tm3_sram_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
					
					      
					when "101" =>
						
						tm3_sram_addr <= vidin_addr_buf_sc_1;
						tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= vidin_data_buf_sc_1;
					
					
					when "110" => 
						 if vert(8)= '0' then
					        tm3_sram_addr <= "00000" & vert(7 downto 0) & horiz(8 downto 3);					
			                        tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
					
					        else 
						tm3_sram_addr <= "00001" & vert(7 downto 0) & horiz(8 downto 3);					
						tm3_sram_we <= "11111111";
						tm3_sram_oe <= "11";
						tm3_sram_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
					
					        end if; 
					
					when "111" =>
						--vidout_buf <= tm3_sram_data;
						tm3_sram_addr <= vidin_addr_buf_sc_1;
                                                -- changed in test_brw_fast_...._als_im, jul 29
						tm3_sram_we <= "11111111"; --"00000000"; --"11111111"; --"00000000";
						tm3_sram_oe <= "11";
						tm3_sram_data <= vidin_data_buf_sc_1;
					
					end case;
			end if;


			if (vidin_new_data_fifo = '1')   then  
			
		   	 case vidin_addr_reg_reg(2 downto 0) is
				when "000" =>
					vidin_data_buf_2_sc_1(7 downto 0) <= vidin_rgb_reg_tmp;	
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(7 downto 0);
					vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(7 downto 0);
					
				when "001" =>
					vidin_data_buf_2_sc_1(15 downto 8) <= vidin_rgb_reg_tmp;
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(15 downto 8);
					vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(15 downto 8);
					
				when "010" =>
					vidin_data_buf_2_sc_1(23 downto 16) <= vidin_rgb_reg_tmp;
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(23 downto 16);	
					vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(23 downto 16);	
					
				when "011" =>
					vidin_data_buf_2_sc_1(31 downto 24) <= vidin_rgb_reg_tmp;
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(31 downto 24);
					vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(31 downto 24);
					
				when "100" =>
					vidin_data_buf_2_sc_1(39 downto 32) <= vidin_rgb_reg_tmp;
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(39 downto 32);
					vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(39 downto 32);
					
				when "101" =>
					vidin_data_buf_2_sc_1(47 downto 40) <= vidin_rgb_reg_tmp;
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(47 downto 40);
					vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(47 downto 40);
					
				when "110" =>
					vidin_data_buf_2_sc_1(55 downto 48) <= vidin_rgb_reg_tmp;
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(55 downto 48);
			  		vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(55 downto 48);
			  	
				when "111" =>
				    vidin_data_buf_sc_1 <= vidin_rgb_reg_tmp &
					vidin_data_buf_2_sc_1(55 downto 0);
					
					--vidout_buf_fifo_2_1 <= vidout_buf_fifo_1;
					vidout_buf_fifo_2_1_left <= vidout_buf_fifo_1_left;
					vidout_buf_fifo_2_1_right <= vidout_buf_fifo_1_right;
					
					vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left(63 downto 56);
			     	vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right(63 downto 56);
			     
			       
					vidin_addr_buf_sc_1 <= "0000" & svid_comp_switch 
								& vidin_addr_reg_reg(16 downto 3);
				-----------------------------------------------------------
					if vidin_addr_reg_reg(8 downto 3)= 43 then
							vidin_addr_buf_sc_1_fifo <= (vidin_addr_reg_reg(16 downto 9) + "00000001") & "000000";
					else
						if vidin_addr_reg_reg(8 downto 3)= 44 then
								vidin_addr_buf_sc_1_fifo <= (vidin_addr_reg_reg(16 downto 9) + "00000001") & "000001";
						else 	
							vidin_addr_buf_sc_1_fifo <= (vidin_addr_reg_reg(16 downto 3)) + 2;
						end if;
					end if;
				-----------------------------------------------------------
				
		end case;


		--vidin_rgb_reg_tmp <= vidin_rgb_reg(7 downto 0);
		--vidin_addr_reg_2to3 <= vidin_addr_reg;
		--vidin_rgb_reg_fifo_left <=  vidin_data_buf_fifo_sc_1; --xor vidin_rgb_reg_tmp;
		--vidin_rgb_reg_fifo_right <=  vidin_rgb_reg_tmp;	--vidin_data_buf_fifo_sc_1; -- 	
       		
			end if;

		--vidin_new_data_fifo <= vidin_new_data;
		--svid_comp_switch_2to3 <= svid_comp_switch;



		end if;
	end process;

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 ='1') then 
	
			vidin_rgb_reg_tmp <= vidin_rgb_reg;
			
			vidin_addr_reg_2to3 <= vidin_addr_reg;
			
			vidin_addr_reg_reg <= vidin_addr_reg;
			vidin_addr_reg_2to0 <= vidin_addr_reg(1 downto 0) & vidin_addr_reg(10 downto 9);


			--vidin_new_data_tmp <= vidin_new_data;
			vidin_new_data_fifo <= vidin_new_data;  --_tmp;
			
			
			--vidin_new_data_fifo <= vidin_new_data;
			
			svid_comp_switch_2to3 <= svid_comp_switch;

			--vidin_rgb_reg_fifo_left <= vidin_rgb_reg_fifo_left_32;
			--vidin_rgb_reg_fifo_right <= vidin_rgb_reg_fifo_right_32;
			
			--vidin_rgb_reg_fifo_left_23 <= vidin_data_buf_fifo_sc_1_l; --"11111111"; -- --xor vidin_rgb_reg_tmp;
			--vidin_rgb_reg_fifo_right_23 <= vidin_data_buf_fifo_sc_1_r; --vidin_rgb_reg_tmp;	--vidin_data_buf_fifo_sc_1; -- 	
 
			vidin_rgb_reg_fifo_left <= vidin_data_buf_fifo_sc_1_l;
			vidin_rgb_reg_fifo_right <= vidin_data_buf_fifo_sc_1_r;

			v_nd_s1_left <= v_nd_s1_left_2to0;
			v_nd_s2_left <= v_nd_s2_left_2to0;
			v_nd_s4_left <= v_nd_s4_left_2to0;
			v_d_reg_s1_left <= v_d_reg_s1_left_2to0; 
			v_d_reg_s2_left <= v_d_reg_s2_left_2to0; 
			v_d_reg_s4_left <= v_d_reg_s4_left_2to0; 
			v_nd_s1_right <= v_nd_s1_right_2to0;
			v_nd_s2_right <= v_nd_s2_right_2to0;
			v_nd_s4_right <= v_nd_s4_right_2to0;
			v_d_reg_s1_right <= v_d_reg_s1_right_2to0; 
			v_d_reg_s2_right <= v_d_reg_s2_right_2to0; 
			v_d_reg_s4_right <= v_d_reg_s4_right_2to0; 

  		end if;
	end process;    				

end arch_sv_chip2;