sv_chip2.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sv_chip2 is port(
	tm3_clk_v0: in std_logic;
	tm3_sram_data : inout std_logic_vector(63 downto 0);
	tm3_sram_addr : out std_logic_vector(18 downto 0);
	tm3_sram_we : out std_logic_vector(7 downto 0);
	tm3_sram_oe : out std_logic_vector(1 downto 0);
	tm3_sram_adsp : out std_logic;
	vidin_new_data: in std_logic;
	vidin_rgb_reg: in std_logic_vector(7 downto 0);
	vidin_addr_reg: in std_logic_vector(18 downto 0);
	svid_comp_switch : in std_logic;
	counter_out_2to1: out std_logic_vector(2 downto 0);
	bus_word_3_2to1: out std_logic_vector(15 downto 0);
	bus_word_4_2to1: out std_logic_vector(15 downto 0);
	bus_word_5_2to1: out std_logic_vector(15 downto 0);
	bus_word_6_2to1: out std_logic_vector(15 downto 0);
	vidin_new_data_fifo: out std_logic;
	vidin_rgb_reg_fifo_left:out std_logic_vector(7 downto 0);
	vidin_rgb_reg_fifo_right:  out std_logic_vector(7 downto 0);
	vidin_addr_reg_2to0: out std_logic_vector(3 downto 0);
	v_nd_s1_left_2to0: in std_logic;     
	v_nd_s2_left_2to0 :in std_logic;
	v_nd_s4_left_2to0 :in std_logic;
	v_d_reg_s1_left_2to0 :in std_logic_vector(7 downto 0);    
	v_d_reg_s2_left_2to0 :in std_logic_vector(7 downto 0);
	v_d_reg_s4_left_2to0 :in std_logic_vector(7 downto 0);
	v_nd_s1_right_2to0: in std_logic;     
	v_nd_s2_right_2to0 :in std_logic;
	v_nd_s4_right_2to0 :in std_logic;
	v_d_reg_s1_right_2to0 :in std_logic_vector(7 downto 0);    
	v_d_reg_s2_right_2to0 :in std_logic_vector(7 downto 0);
	v_d_reg_s4_right_2to0 :in std_logic_vector(7 downto 0));
	
	
end sv_chip2;

architecture arch_sv_chip2 of sv_chip2 is
	signal v_nd_s1: std_logic;
	signal vidin_new_data_v_fltr: std_logic;
	signal horiz: std_logic_vector(9 downto 0);
	signal vert: std_logic_vector(9 downto 0);
	signal vidin_data_buf_sc_1 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_1 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_1 : std_logic_vector(18 downto 0);
	signal vidin_addr_buf_sc_1_fifo : std_logic_vector(13 downto 0);
	signal vidin_addr_reg_scld: std_logic_vector(18 downto 0);
	signal video_state : std_logic;
	signal vidin_gray_scld_1: std_logic_vector(7 downto 0);
	signal vidout_buf_fifo_1_left:std_logic_vector(63 downto 0);
	signal vidout_buf_fifo_1_right:std_logic_vector(63 downto 0);
	signal vidin_rgb_reg_tmp: std_logic_vector(7 downto 0);
	signal vidin_data_buf_fifo_sc_1_l: std_logic_vector(7 downto 0);
	signal vidin_data_buf_fifo_sc_1_r: std_logic_vector(7 downto 0);
	signal vidout_buf_fifo_2_1_left: std_logic_vector(63 downto 0); 
	signal vidout_buf_fifo_2_1_right: std_logic_vector(63 downto 0); 
	signal vidin_new_data_tmp: std_logic;
	signal vidin_addr_reg_reg : std_logic_vector(18 downto 0);
	signal v_nd_s1_left,v_nd_s1_right: std_logic;
	signal v_nd_s2_left,v_nd_s2_right: std_logic;
	signal v_nd_s4_left,v_nd_s4_right: std_logic;
	signal v_d_reg_s1_left,v_d_reg_s1_right: std_logic_vector(7 downto 0);
	signal v_d_reg_s2_left, v_d_reg_s2_right: std_logic_vector(7 downto 0);
	signal v_d_reg_s4_left, v_d_reg_s4_right: std_logic_vector(7 downto 0);
	signal vidin_v_out_1_f1_left,vidin_v_out_1_f2_left,vidin_v_out_1_f3_left,vidin_v_out_1_h1_left
		,vidin_v_out_1_h2_left,vidin_v_out_1_h3_left,vidin_v_out_1_h4_left: std_logic_vector(15 downto 0);
	signal vidin_v_out_2_f1_left,vidin_v_out_2_f2_left,vidin_v_out_2_f3_left,vidin_v_out_2_h1_left
		,vidin_v_out_2_h2_left,vidin_v_out_2_h3_left,vidin_v_out_2_h4_left: std_logic_vector(15 downto 0);
	signal vidin_v_out_4_f1_left,vidin_v_out_4_f2_left,vidin_v_out_4_f3_left,vidin_v_out_4_h1_left
		,vidin_v_out_4_h2_left,vidin_v_out_4_h3_left,vidin_v_out_4_h4_left: std_logic_vector(15 downto 0);
	signal vidin_v_out_1_f1_right,vidin_v_out_1_f2_right,vidin_v_out_1_f3_right,vidin_v_out_1_h1_right
		,vidin_v_out_1_h2_right,vidin_v_out_1_h3_right,vidin_v_out_1_h4_right: std_logic_vector(15 downto 0);
	signal vidin_v_out_2_f1_right,vidin_v_out_2_f2_right,vidin_v_out_2_f3_right,vidin_v_out_2_h1_right
		,vidin_v_out_2_h2_right,vidin_v_out_2_h3_right,vidin_v_out_2_h4_right: std_logic_vector(15 downto 0);
	signal vidin_v_out_4_f1_right,vidin_v_out_4_f2_right,vidin_v_out_4_f3_right,vidin_v_out_4_h1_right
		,vidin_v_out_4_h2_right,vidin_v_out_4_h3_right,vidin_v_out_4_h4_right: std_logic_vector(15 downto 0);	
	signal v_d_reg_s1_2to3_left:  std_logic_vector(7 downto 0);
	signal v_d_reg_s2_2to3_left:  std_logic_vector(7 downto 0);
	signal v_d_reg_s4_2to3_left:  std_logic_vector(7 downto 0);
	signal v_d_reg_s1_2to3_right:  std_logic_vector(7 downto 0);
	signal v_d_reg_s2_2to3_right:  std_logic_vector(7 downto 0);
	signal v_d_reg_s4_2to3_right:  std_logic_vector(7 downto 0);
	signal vidin_addr_reg_2to3:  std_logic_vector(18 downto 0);
	signal svid_comp_switch_2to3: std_logic;
	signal real_z_4_left,imag_z_4_left,real_p_4_left,imag_p_4_left,real_n_4_left,imag_n_4_left: std_logic_vector(15 downto 0);
	signal real_z_4_right,imag_z_4_right,real_p_4_right,imag_p_4_right,real_n_4_right,imag_n_4_right: std_logic_vector(15 downto 0);
	signal real_z_2_left,imag_z_2_left,real_p_2_left,imag_p_2_left,real_n_2_left,imag_n_2_left: std_logic_vector(15 downto 0);
	signal real_z_2_right,imag_z_2_right,real_p_2_right,imag_p_2_right,real_n_2_right,imag_n_2_right: std_logic_vector(15 downto 0);
	signal real_z_1_left,imag_z_1_left,real_p_1_left,imag_p_1_left,real_n_1_left,imag_n_1_left: std_logic_vector(15 downto 0);
	signal real_z_1_right,imag_z_1_right,real_p_1_right,imag_p_1_right,real_n_1_right,imag_n_1_right: std_logic_vector(15 downto 0);


	-- component scaler port(
	--	tm3_clk_v0: in std_logic;
	--	vidin_new_data: in std_logic;
	--	vidin_rgb_reg: in std_logic_vector(7 downto 0);
	--	vidin_addr_reg: in std_logic_vector(18 downto 0);
	--	vidin_new_data_scld_1: out std_logic;
    --	vidin_new_data_scld_2: out std_logic;
  	--	vidin_new_data_scld_4: out std_logic;
	--	vidin_gray_scld_1:out std_logic_vector(7 downto 0);
	--	vidin_gray_scld_2:out std_logic_vector(7 downto 0);
	--	vidin_gray_scld_4:out std_logic_vector(7 downto 0));
	-- end component;

	component h_fltr port(
        	tm3_clk_v0 : in std_logic;
		vidin_new_data : in std_logic;
		vidin_in_f1: in std_logic_vector(15 downto 0);
		vidin_in_f2: in std_logic_vector(15 downto 0);
		vidin_in_f3: in std_logic_vector(15 downto 0);
		vidin_in_h1: in std_logic_vector(15 downto 0);
		vidin_in_h2: in std_logic_vector(15 downto 0);
		vidin_in_h3: in std_logic_vector(15 downto 0);
		vidin_in_h4: in std_logic_vector(15 downto 0);
		real_z_reg: out std_logic_vector(15 downto 0);
		imag_z_reg: out std_logic_vector(15 downto 0);
		real_p_reg: out std_logic_vector(15 downto 0);
		imag_p_reg: out std_logic_vector(15 downto 0);
		real_n_reg: out std_logic_vector(15 downto 0);
		imag_n_reg: out std_logic_vector(15 downto 0));
	end component;
	

	component h_fltr_or port(
        	tm3_clk_v0 : in std_logic;
		vidin_new_data : in std_logic;
		vidin_in: in std_logic_vector(7 downto 0);
		vidin_out_or : out std_logic_vector(7 downto 0));
	end component;


	component v_fltr generic(
		horiz_length : integer;
		vert_length: integer);
		port(
        	tm3_clk_v0 : in std_logic;
		vidin_new_data : in std_logic;
		vidin_in: in std_logic_vector(7 downto 0);
		vidin_out_f1 : out std_logic_vector(15 downto 0);
		vidin_out_f2 : out std_logic_vector(15 downto 0);
		vidin_out_f3 : out std_logic_vector(15 downto 0);
		vidin_out_h1 : out std_logic_vector(15 downto 0);
		vidin_out_h2 : out std_logic_vector(15 downto 0);
		vidin_out_h3 : out std_logic_vector(15 downto 0);
		vidin_out_h4 : out std_logic_vector(15 downto 0);
		vidin_out_or:out std_logic_vector(7 downto 0));
	end component;

	component port_bus_2to1 port(
		clk: in std_logic;
		vidin_addr_reg: in std_logic_vector(18 downto 0);
		svid_comp_switch : in std_logic;
		vidin_new_data_scld_1_2to3_left: in std_logic;
		vidin_data_reg_scld_1_2to3_left_rp: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_left_ip: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_left_rn: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_left_in: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_rp: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_ip: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_rn: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_left_in: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_rp: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_ip: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_rn: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_left_in: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_rp: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_ip: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_rn: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_1_2to3_right_in: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_rp: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_ip: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_rn: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_2_2to3_right_in: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_rp: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_ip: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_rn: in std_logic_vector(15 downto 0);
		vidin_data_reg_scld_4_2to3_right_in: in std_logic_vector(15 downto 0);
		bus_word_3: out std_logic_vector(15 downto 0);
		bus_word_4: out std_logic_vector(15 downto 0);
		bus_word_5: out std_logic_vector(15 downto 0);
		bus_word_6: out std_logic_vector(15 downto 0);
		counter_out: out std_logic_vector(2 downto 0));
end component;

begin




---------------------------------------------------------------------------------------------------------
----------------------  doing scaling , v_fltr and v_fltr on left image ---------------------------------
---------------------------------------------------------------------------------------------------------
	
	--scaler_inst_left: scaler port map(tm3_clk_v0,
	--				vidin_new_data_fifo,
	--				vidin_rgb_reg_fifo_left,
	--				vidin_addr_reg_reg,
	--				v_nd_s1_left,     
	--				v_nd_s2_left,
	--				v_nd_s4_left,
	--				v_d_reg_s1_left,    
	--				v_d_reg_s2_left,
	--				v_d_reg_s4_left);

	
	
	v_fltr_1_left: v_fltr generic map(496,7) --16)  --10)
		port map(tm3_clk_v0,
				v_nd_s1_left,    
				v_d_reg_s1_left,					
				vidin_v_out_1_f1_left,
				vidin_v_out_1_f2_left,
				vidin_v_out_1_f3_left,
				vidin_v_out_1_h1_left,
				vidin_v_out_1_h2_left,
				vidin_v_out_1_h3_left,
				vidin_v_out_1_h4_left,
				open);							


	v_fltr_2_left: v_fltr generic map(316,7) --13)   --,7)
		port map(tm3_clk_v0,
				v_nd_s2_left,    
				v_d_reg_s2_left,		
				vidin_v_out_2_f1_left,
				vidin_v_out_2_f2_left,
				vidin_v_out_2_f3_left,
				vidin_v_out_2_h1_left,
				vidin_v_out_2_h2_left,
				vidin_v_out_2_h3_left,
				vidin_v_out_2_h4_left,
				open);							

	v_fltr_4_left: v_fltr generic map(226,7)
		port map(tm3_clk_v0,
				v_nd_s4_left,    
				v_d_reg_s4_left,		
				vidin_v_out_4_f1_left,
				vidin_v_out_4_f2_left,
				vidin_v_out_4_f3_left,
				vidin_v_out_4_h1_left,
				vidin_v_out_4_h2_left,
				vidin_v_out_4_h3_left,
				vidin_v_out_4_h4_left,
				open);							

	
	
	


	h_fltr_1_left: h_fltr port map(tm3_clk_v0,
				v_nd_s1_left,  	
				vidin_v_out_1_f1_left,
				vidin_v_out_1_f2_left,
				vidin_v_out_1_f3_left,
				vidin_v_out_1_h1_left,
				vidin_v_out_1_h2_left,
				vidin_v_out_1_h3_left,
				vidin_v_out_1_h4_left,
				real_z_1_left, 
				imag_z_1_left,
				real_p_1_left,
				imag_p_1_left,
                real_n_1_left,
				imag_n_1_left);

				
	h_fltr_2_left: h_fltr port map(tm3_clk_v0,
				v_nd_s2_left,  	
				vidin_v_out_2_f1_left,
				vidin_v_out_2_f2_left,
				vidin_v_out_2_f3_left,
				vidin_v_out_2_h1_left,
				vidin_v_out_2_h2_left,
				vidin_v_out_2_h3_left,
				vidin_v_out_2_h4_left,
				real_z_2_left, 
				imag_z_2_left,
				real_p_2_left,
				imag_p_2_left,
                real_n_2_left,
				imag_n_2_left);

				
	h_fltr_4_left: h_fltr port map(tm3_clk_v0,
				v_nd_s4_left,  
				vidin_v_out_4_f1_left,
				vidin_v_out_4_f2_left,
				vidin_v_out_4_f3_left,
				vidin_v_out_4_h1_left,
				vidin_v_out_4_h2_left,
				vidin_v_out_4_h3_left,
				vidin_v_out_4_h4_left,
				real_z_4_left, 
				imag_z_4_left,
				real_p_4_left,
				imag_p_4_left,
                real_n_4_left,
				imag_n_4_left);

---------------------------------------------------------------------------------------------------------
----------------------  doing scaling , v_fltr and v_fltr on right image ---------------------------------
---------------------------------------------------------------------------------------------------------
	
	
	--scaler_inst_right: scaler port map(tm3_clk_v0,
	--				vidin_new_data_fifo,
	--				vidin_rgb_reg_fifo_right,
	--				vidin_addr_reg_reg,
	--				v_nd_s1_right,  	
	--				v_nd_s2_right,
	--				v_nd_s4_right,
	--				v_d_reg_s1_right,  
	--				v_d_reg_s2_right,
	--				v_d_reg_s4_right);


	v_fltr_1_right: v_fltr generic map(496,7)   --16)   --,10)
		port map(tm3_clk_v0,
				v_nd_s1_right,    
				v_d_reg_s1_right,					
				vidin_v_out_1_f1_right,
				vidin_v_out_1_f2_right,
				vidin_v_out_1_f3_right,
				vidin_v_out_1_h1_right,
				vidin_v_out_1_h2_right,
				vidin_v_out_1_h3_right,
				vidin_v_out_1_h4_right,
				open);							

	v_fltr_2_right: v_fltr generic map(316,7)  --13)   --,7)
		port map(tm3_clk_v0,
				v_nd_s2_right,    
				v_d_reg_s2_right,		
				vidin_v_out_2_f1_right,
				vidin_v_out_2_f2_right,
		    	vidin_v_out_2_f3_right,
				vidin_v_out_2_h1_right,
				vidin_v_out_2_h2_right,
				vidin_v_out_2_h3_right,
				vidin_v_out_2_h4_right,
				open);							

	v_fltr_4_right: v_fltr generic map(226,7)
		port map(tm3_clk_v0,
				v_nd_s4_right,    
				v_d_reg_s4_right,		
				vidin_v_out_4_f1_right,
				vidin_v_out_4_f2_right,
				vidin_v_out_4_f3_right,