sv_chip0.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

					v_d_reg_s1_right_2to0_tmp,  
					v_d_reg_s2_right_2to0_tmp,
					v_d_reg_s4_right_2to0_tmp);

	v_fltr_496_l_inst: v_fltr_496 generic map(12)
					port map(
						tm3_clk_v0,
						v_nd_s1_left_2to0_tmp,
						v_d_reg_s1_left_2to0_tmp,
						v_d_reg_s1_left_2to0_fifo_tmp);

	v_fltr_496_r_inst: v_fltr_496 generic map(12)
					port map(
						tm3_clk_v0,
						v_nd_s1_right_2to0_tmp,
						v_d_reg_s1_right_2to0_tmp,
						v_d_reg_s1_right_2to0_fifo_tmp);

	v_fltr_316_l_inst: v_fltr_316 generic map(4)
					port map(
						tm3_clk_v0,
						v_nd_s2_left_2to0_tmp,
						v_d_reg_s2_left_2to0_tmp,
						v_d_reg_s2_left_2to0_fifo_tmp);

	v_fltr_316_r_inst: v_fltr_316 generic map(4)
					port map(
						tm3_clk_v0,
						v_nd_s2_right_2to0_tmp,
						v_d_reg_s2_right_2to0_tmp,
						v_d_reg_s2_right_2to0_fifo_tmp);

--------------------------------------------------------------------------------
--------------------------------------------------------------------------------


port_bus_1to0_1_inst: port_bus_1to0_1 generic map(8)
	port map(
		tm3_clk_v0,
		vidin_addr_reg,
		svid_comp_switch_2to3,
		vidin_new_data_scld_1_1to0,
		v_corr_20,
		vidin_new_data_scld_2_1to0,
		v_corr_10,
		vidin_new_data_scld_4_1to0,
		v_corr_05,
		bus_word_1_1to0,
		bus_word_2_1to0,
		bus_word_3_1to0,
		bus_word_4_1to0,
		bus_word_5_1to0,
		bus_word_6_1to0,
		counter_out_1to0);



----------------------------------------------------------------------------
---------------- LP Horiz. fltr of the correlation results ----------------- 
----------------------------------------------------------------------------

	gen_fir_1: for i in 0 to 20 generate
					inst_fir_1: lp_fltr
								port map(
										tm3_clk_v0,
										v_corr_20(i),
										v_corr_20_fltr_h(i),
										vidin_new_data_scld_1_1to0);
	end generate;


	
	gen_fir_2: for i in 0 to 10 generate
					inst_fir_2: lp_fltr
								port map(
										tm3_clk_v0,
										v_corr_10(i),
										v_corr_10_fltr_h(i),
										vidin_new_data_scld_2_1to0);
	end generate;


		

	gen_fir_4: for i in 0 to 5 generate
					inst_fir_4: lp_fltr
								port map(
										tm3_clk_v0,
										v_corr_05(i),
										v_corr_05_fltr_h(i),
										vidin_new_data_scld_4_1to0);
	end generate;
	
----------------------------------------------------------------------------
---------------- LP Vert. fltr of the correlation results ----------------- 
----------------------------------------------------------------------------
	gen_fir_1_v: for i in 0 to 20 generate
				inst_fir_v1: lp_fltr_v1
								port map(
										tm3_clk_v0,
										v_corr_20_fltr_h(i),
										v_corr_20_fltr_x(i),
										v_corr_20_fltr(i),
										vidin_new_data_scld_1_1to0);
					
	end generate;

	gen_fir_1_v: for i in 0 to 10 generate
				inst_fir_v2: lp_fltr_v2
								port map(
										tm3_clk_v0,
										v_corr_10_fltr_h(i),
										v_corr_10_fltr_x(i),
										v_corr_10_fltr(i),
										vidin_new_data_scld_2_1to0);
	end generate;

	gen_fir_1_v: for i in 0 to 5 generate
				inst_fir_v4: lp_fltr_v4
								port map(
										tm3_clk_v0,
										v_corr_05_fltr_h(i),
										v_corr_05_fltr_x(i),
										v_corr_05_fltr(i),
										vidin_new_data_scld_4_1to0);
	end generate;

	
----------------------------------------------------------------------------
-------------- back interpolation from scale 2 and 4 to scale 1 ------------
----------------------------------------------------------------------------

wrapper_qs_intr_inst_5: wrapper_qs_intr_5_20
	port map(
		tm3_clk_v0,
		v_corr_05_fltr,
		vidin_new_data_scld_1_1to0,
		vidin_new_data_scld_4_1to0,
		vidin_addr_reg,
		qs_4_out,
		rdy_4_out);

wrapper_qs_intr_inst_10: wrapper_qs_intr_10_20
	port map(
		tm3_clk_v0,
		v_corr_10_fltr,
		vidin_new_data_scld_1_1to0,
		vidin_new_data_scld_2_1to0,
		vidin_addr_reg,
		qs_2_out,
		rdy_2_out);


wrapper_qs_intr_inst_5_more: wrapper_qs_intr_5_20
	port map(
		tm3_clk_v0,
		v_corr_05_fltr_x,
		vidin_new_data_scld_1_1to0,
		vidin_new_data_scld_4_1to0,
		vidin_addr_reg,
		qs_4_out_x,
		open);

wrapper_qs_intr_inst_10_more: wrapper_qs_intr_10_20
	port map(
		tm3_clk_v0,
		v_corr_10_fltr_x,
		vidin_new_data_scld_1_1to0,
		vidin_new_data_scld_2_1to0,
		vidin_addr_reg,
		qs_2_out_x,
		open);

------------------------------------------------------------------------------
--------------------------- end of back interpolation ------------------------
------------------------------------------------------------------------------

------------------------------------------------------------------------------
-----------------  horiz. delay unit for scale 1 and 2 to allign with sc_4 ---
------------------------------------------------------------------------------

	gen_1_1 : for i in 0 to 20 generate
				ints_fifo_1_gen_1 : my_fifo_1 
								port map(
									tm3_clk_v0,
									v_corr_20_fltr(i),
									v_corr_20_fifo(i),
									rdy_4_out);
	end generate;



	gen_2_1 : for i in 0 to 20 generate
				ints_fifo_2_gen_1 : my_fifo_2 
								port map(
									tm3_clk_v0,
									qs_2_out(i)(8 downto 0), --(8 downto 1),
									v_corr_10_fifo(i),
									rdy_4_out);
	end generate;


--------------------------- end of horiz. delay units ----------------------
----------------------------------------------------------------------------

-------------------------------------------------------------------------------------------
-----------------------------      combining scales ---------------------------------------

	gen_combine : for i in 0 to 20 generate
		combine_res_inst : combine_res
				port map(
					tm3_clk_v0,
					rdy_4_out,
					v_corr_20_fifo(i),
					v_corr_10_fifo(i),
					qs_4_out(i)(8 downto 0),
					comb_out(i));	
	end generate;
--------------------------------   end of combining ---------------------------------------
-------------------------------------------------------------------------------------------



find_max_inst: find_max 
	port map(
		tm3_clk_v0,
		rdy_4_out,
		comb_out,
		max_data_out,
		max_indx_out);

	

	-------------------------------------------------------------------------------------------
	------------------------------ writing data to SRAM ---------------------------------------

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then		
			vidin_new_data_scld_1_2to3_left_reg <= rdy_4_out; --vidin_new_data_scld_1_1to0;
			vidin_new_data_scld_2_2to3_left_reg <= rdy_4_out; --vidin_new_data_scld_2_1to0;
			vidin_new_data_scld_4_2to3_left_reg <= rdy_4_out; --vidin_new_data_scld_4_1to0;
			vidin_data_reg_scld_1_2to3_left_reg <= v_corr_20_fifo(0);--qs_4_out(1)(8 downto 1);  --(0);
			vidin_data_reg_scld_1_2to3_right_reg <= v_corr_10_fifo(0)(8 downto 1); --comb_out(0)(8 downto 1); --v_corr_20_fifo(5); --(5);
			vidin_data_reg_scld_2_2to3_left_reg <=  qs_4_out(0)(8 downto 1); --comb_out(1)(8 downto 1); --qs_2_out(0)(8 downto 1); --v_corr_10(0);
			vidin_data_reg_scld_2_2to3_right_reg <= comb_out(0)(8 downto 1);--"000" & max_indx_out; --qs_2_out(5)(8 downto 1);  --v_corr_10(5);
			vidin_data_reg_scld_4_2to3_left_reg <= comb_out(4)(8 downto 1);--qs_4_out(1)(8 downto 1); --v_corr_05(0);
			vidin_data_reg_scld_4_2to3_right_reg <= max_indx_out & "000"; --"000" & max_indx_out; --v_corr_10_fifo(4)(8 downto 1);--comb_out(10)(10 downto 3); --qs_4_out(5)(8 downto 1); --v_corr_05(5);
		
	

			if (vidin_addr_reg(8 downto 0) >= "001001000") then
				vidin_addr_reg_2to3_reg <= vidin_addr_reg - "0000000000001001000";  -- addr-72
			else
				vidin_addr_reg_2to3_reg <= vidin_addr_reg + "0000000000100100000";  -- addr-72+360
			end if;

		end if;
	end process;
		
	------------------------------- end of witing to SRAM -------------------------------------
	-------------------------------------------------------------------------------------------
	
	-------------------------------------------------------------------------------------------
    ------------------------       sending back the delayed signal to chip 2 ------------------
	

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then		
	
			v_nd_s1_left_2to0 <= v_nd_s1_left_2to0_tmp;     
			v_nd_s2_left_2to0 <= v_nd_s2_left_2to0_tmp;
			v_nd_s4_left_2to0 <= v_nd_s4_left_2to0_tmp;
		
			v_nd_s1_right_2to0 <= v_nd_s1_right_2to0_tmp;  	
			v_nd_s2_right_2to0 <= v_nd_s2_right_2to0_tmp;
			v_nd_s4_right_2to0 <= v_nd_s4_right_2to0_tmp;
		
			if v_nd_s1_left_2to0_tmp = '1' then
					v_d_reg_s1_left_2to0 <= v_d_reg_s1_left_2to0_fifo_tmp;
					v_d_reg_s1_right_2to0 <= v_d_reg_s1_right_2to0_fifo_tmp;
			end if;

			if v_nd_s2_left_2to0_tmp = '1' then
					v_d_reg_s2_left_2to0 <= v_d_reg_s2_left_2to0_fifo_tmp;
					v_d_reg_s2_right_2to0 <= v_d_reg_s2_right_2to0_fifo_tmp;
			end if;

			if v_nd_s4_left_2to0_tmp = '1' then
					v_d_reg_s4_left_2to0 <= v_d_reg_s4_left_2to0_tmp;
					v_d_reg_s4_right_2to0 <= v_d_reg_s4_right_2to0_tmp;
			end if;
		end if;
	end process;
		
	-------------------------------  end of sending back ---------------------------------------
	--------------------------------------------------------------------------------------------

	tm3_vidout_clock <= not(video_state);

	process(tm3_clk_v0) begin
		if (tm3_clk_v0'event and tm3_clk_v0 = '1') then
			x_reg_l <= x_in;
			y_reg_up <= y_in;
			x_reg_r <= x_in + 8;
			y_reg_dn <= y_in +8;
			depth_out <= "00000000" & depth_out_reg;

			video_state <= not(video_state);
			
			if video_state = '0' then
				if horiz = 800 then
					horiz <= "0000000000";
					if vert = 525 then
						vert <= "0000000000";
					else
						vert <= vert + 1;
					end if;
				else
					horiz <= horiz + 1;
				end if;
				
				if ((vert >= 491) AND (vert <= 493)) then
					tm3_vidout_vsync <= '1';
				else