sv_chip0.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

-- Ahmad Darabiha
-- last updated Aug, 2002

-- this is the design for chip#0 of 
-- the stereo vision system.
-- this is the last stage which interpolates the results of correlation 
-- and after LPF it takes the Max and send the final results to chip #3 to
-- be displayed on the monitor.
 
library ieee;
use work.basic_type.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sv_chip0 is port(
	tm3_clk_v0: in std_logic;
	tm3_sram_data : inout std_logic_vector(63 downto 0);
	tm3_sram_addr : out std_logic_vector(18 downto 0);
	tm3_sram_we : out std_logic_vector(7 downto 0);
	tm3_sram_oe : out std_logic_vector(1 downto 0);
	tm3_sram_adsp : out std_logic;
	bus_word_1_1to0: in std_logic_vector(7 downto 0);
	bus_word_2_1to0: in std_logic_vector(7 downto 0);
	bus_word_3_1to0: in std_logic_vector(7 downto 0);
	bus_word_4_1to0: in std_logic_vector(7 downto 0);
	bus_word_5_1to0: in std_logic_vector(7 downto 0);
	bus_word_6_1to0: in std_logic_vector(7 downto 0);
	counter_out_1to0: in std_logic_vector(2 downto 0);
	vidin_new_data_fifo: in std_logic;
	vidin_rgb_reg_fifo_left:in std_logic_vector(7 downto 0);
	vidin_rgb_reg_fifo_right:in std_logic_vector(7 downto 0);
	vidin_addr_reg_2to0: in std_logic_vector(3 downto 0);
	v_nd_s1_left_2to0: out std_logic;     
	v_nd_s2_left_2to0 : out std_logic;
	v_nd_s4_left_2to0 : out std_logic;
	v_d_reg_s1_left_2to0 : out std_logic_vector(7 downto 0);    
	v_d_reg_s2_left_2to0 :out std_logic_vector(7 downto 0);
	v_d_reg_s4_left_2to0 :out std_logic_vector(7 downto 0);
	v_nd_s1_right_2to0: out std_logic;     
	v_nd_s2_right_2to0 : out std_logic;
	v_nd_s4_right_2to0 : out std_logic;
	v_d_reg_s1_right_2to0 : out std_logic_vector(7 downto 0);    
	v_d_reg_s2_right_2to0 :out std_logic_vector(7 downto 0);
	v_d_reg_s4_right_2to0 :out std_logic_vector(7 downto 0);
	tm3_vidout_red,tm3_vidout_green,tm3_vidout_blue : out std_logic_vector( 9 downto 0);
 	tm3_vidout_clock,tm3_vidout_hsync,tm3_vidout_vsync,tm3_vidout_blank : out std_logic;
	x_in: in std_logic_vector(15 downto 0);
	y_in: in std_logic_vector(15 downto 0);
	depth_out : out std_logic_vector(15 downto 0));
end sv_chip0;

architecture arch_sv_chip0 of sv_chip0 is
	signal x_reg_l,x_reg_r,y_reg_up,y_reg_dn : std_logic_vector(15 downto 0);
	signal depth_out_reg : std_logic_vector(7 downto 0);
	signal horiz: std_logic_vector(9 downto 0);
	signal vert: std_logic_vector(9 downto 0);
	signal vidin_data_buf_sc_1 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_1 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_1 : std_logic_vector(18 downto 0);
	signal vidout_buf : std_logic_vector(63 downto 0);
	signal vidin_data_buf_sc_2 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_2 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_2 : std_logic_vector(18 downto 0);
	signal vidin_data_buf_sc_4 : std_logic_vector(63 downto 0);
	signal vidin_data_buf_2_sc_4 : std_logic_vector(55 downto 0);
	signal vidin_addr_buf_sc_4 : std_logic_vector(18 downto 0);
	signal video_state : std_logic;
	signal vidin_new_data_scld_1_2to3_left_reg: std_logic;
	signal vidin_data_reg_scld_1_2to3_left_reg: std_logic_vector(7 downto 0);
	signal vidin_data_reg_scld_1_2to3_right_reg: std_logic_vector(7 downto 0);
	signal vidin_new_data_scld_2_2to3_left_reg: std_logic;
	signal vidin_data_reg_scld_2_2to3_left_reg: std_logic_vector(7 downto 0);
	signal vidin_data_reg_scld_2_2to3_right_reg: std_logic_vector(7 downto 0);
	signal vidin_new_data_scld_4_2to3_left_reg: std_logic;
	signal vidin_data_reg_scld_4_2to3_left_reg: std_logic_vector(7 downto 0);
	signal vidin_data_reg_scld_4_2to3_right_reg: std_logic_vector(7 downto 0);
	
	signal vidin_addr_reg_2to3_reg: std_logic_vector(18 downto 0);
	
	signal vidin_addr_reg: std_logic_vector(18 downto 0);
	signal svid_comp_switch_2to3: std_logic;
	signal vidin_new_data_scld_1_1to0: std_logic;
	signal vidin_new_data_scld_2_1to0: std_logic;
	signal vidin_new_data_scld_4_1to0: std_logic;

	signal v_corr_20: type_array_8_20;
	signal v_corr_10: type_array_8_10;
	signal v_corr_05: type_array_8_5;

	signal v_corr_20_fltr: type_array_8_20;
	signal v_corr_10_fltr: type_array_8_10;
	signal v_corr_05_fltr: type_array_8_5;

	signal v_corr_20_fltr_x: type_array_8_20;
	signal v_corr_10_fltr_x: type_array_8_10;
	signal v_corr_05_fltr_x: type_array_8_5;

	signal v_corr_20_fltr_h: type_array_8_20;
	signal v_corr_10_fltr_h: type_array_8_10;
	signal v_corr_05_fltr_h: type_array_8_5;

	signal v_corr_20_fifo: type_array_8_20;
	signal v_corr_10_fifo: type_array_9_20;

	signal v_corr_20_fifo_x: type_array_8_20;
	signal v_corr_10_fifo_x: type_array_9_20;
	
	signal qs_4_out : type_array_16_20;
	signal qs_2_out : type_array_16_20;

	signal qs_4_out_x : type_array_16_20;
	signal qs_2_out_x : type_array_16_20;

	signal rdy_4_out :std_logic;
	signal rdy_2_out :std_logic;

	signal max_data_out: std_logic_vector(7 downto 0);
	signal max_indx_out: std_logic_vector(4 downto 0);

	signal v_nd_s1_left_2to0_tmp: std_logic;     
	signal v_nd_s2_left_2to0_tmp : std_logic;
	signal v_nd_s4_left_2to0_tmp : std_logic;
	signal v_d_reg_s1_left_2to0_tmp : std_logic_vector(7 downto 0);    
	signal v_d_reg_s2_left_2to0_tmp : std_logic_vector(7 downto 0);
	signal v_d_reg_s4_left_2to0_tmp : std_logic_vector(7 downto 0);
	signal v_d_reg_s1_left_2to0_fifo_tmp : std_logic_vector(7 downto 0);    
	signal v_d_reg_s2_left_2to0_fifo_tmp : std_logic_vector(7 downto 0);
	signal v_d_reg_s4_left_2to0_fifo_tmp : std_logic_vector(7 downto 0);
	signal v_nd_s1_right_2to0_tmp: std_logic;     
	signal v_nd_s2_right_2to0_tmp : std_logic;
	signal v_nd_s4_right_2to0_tmp : std_logic;
	signal v_d_reg_s1_right_2to0_tmp : std_logic_vector(7 downto 0);    
	signal v_d_reg_s2_right_2to0_tmp : std_logic_vector(7 downto 0);
	signal v_d_reg_s4_right_2to0_tmp : std_logic_vector(7 downto 0);
	signal v_d_reg_s1_right_2to0_fifo_tmp : std_logic_vector(7 downto 0);    
	signal v_d_reg_s2_right_2to0_fifo_tmp : std_logic_vector(7 downto 0);
	signal v_d_reg_s4_right_2to0_fifo_tmp : std_logic_vector(7 downto 0);

	signal comb_out : type_array_11_20;

	
	component combine_res is 
		port(
		clk : in std_logic;
		wen: in std_logic;
		din_1: in std_logic_vector(7 downto 0);  -- scale_1 is 8 bite wide
		din_2: in std_logic_vector(8 downto 0); -- scale 2 and 4 are 9 bit wide
		din_3: in std_logic_vector(8 downto 0);
		dout: out std_logic_vector(10 downto 0)); 
	end component;

	component v_fltr_496 generic(vert_length : integer);
		port(
    	tm3_clk_v0 : in std_logic;
		vidin_new_data : in std_logic;
		vidin_in : in std_logic_vector(7 downto 0);
		vidin_out : out std_logic_vector(7 downto 0));
	end component;


	component v_fltr_316 generic(vert_length : integer);
		port(
    	tm3_clk_v0 : in std_logic;
		vidin_new_data : in std_logic;
		vidin_in : in std_logic_vector(7 downto 0);
		vidin_out : out std_logic_vector(7 downto 0));
	end component;

	component lp_fltr_v1 port(
		clk: in std_logic;
		din: in std_logic_vector(fltr_din_w-1 downto 0);
		dout_1: out std_logic_vector(fltr_din_w-1 downto 0);
		dout_2: out std_logic_vector(fltr_din_w-1 downto 0);
		nd: in std_logic);
	end component;

	component lp_fltr_v2 port(
		clk: in std_logic;
		din: in std_logic_vector(fltr_din_w-1 downto 0);
		dout_1: out std_logic_vector(fltr_din_w-1 downto 0);
		dout_2: out std_logic_vector(fltr_din_w-1 downto 0);
		nd: in std_logic);
	end component;
	
	component lp_fltr_v4 port(
		clk: in std_logic;
		din: in std_logic_vector(fltr_din_w-1 downto 0);
		dout_1: out std_logic_vector(fltr_din_w-1 downto 0);
		dout_2: out std_logic_vector(fltr_din_w-1 downto 0);
		nd: in std_logic);
	end component;

	component scaler port(
		tm3_clk_v0: in std_logic;
		vidin_new_data: in std_logic;
		vidin_rgb_reg: in std_logic_vector(7 downto 0);
		vidin_addr_reg: in std_logic_vector(3 downto 0);
		vidin_new_data_scld_1: out std_logic;
    	vidin_new_data_scld_2: out std_logic;
  		vidin_new_data_scld_4: out std_logic;
		vidin_gray_scld_1:out std_logic_vector(7 downto 0);
		vidin_gray_scld_2:out std_logic_vector(7 downto 0);
		vidin_gray_scld_4:out std_logic_vector(7 downto 0));
	end component;
	


	component wrapper_qs_intr_5_20 is 
	port(
		clk : in std_logic;
		din: in type_array_8_5;
		wen_1:in std_logic;
		wen_4: in std_logic;
		addrin: in std_logic_vector(18 downto 0);
		dout: out type_array_16_20;
		rdy : out std_logic);
	end component;

	component wrapper_qs_intr_10_20 is 
	port(
		clk : in std_logic;
		din: in type_array_8_10;
		wen_1:in std_logic;
		wen_4: in std_logic;
		addrin: in std_logic_vector(18 downto 0);
		dout: out type_array_16_20;
		rdy : out std_logic);
	end component;


	component find_max port(
		clk: in std_logic;
		wen: in std_logic;
		d_in: type_array_11_20;
		d_out : out std_logic_vector(7 downto 0);
		indx_out : out std_logic_vector(4 downto 0));
	end component;

	component lp_fltr
		port(
		clk: in std_logic;
		din: in std_logic_vector(fltr_din_w-1 downto 0);
		dout: out std_logic_vector(fltr_din_w-1 downto 0);
		ce: in std_logic);
	end component;

	------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
	component my_fifo_1
		port (
		CLK: IN std_logic;
		D: IN std_logic_VECTOR(7 downto 0);
		Q: OUT std_logic_VECTOR(7 downto 0);
		CE: IN std_logic);
	end component;

	-- Synplicity black box declaration
	attribute syn_black_box : boolean;
	attribute syn_black_box of my_fifo_1: component is true;

	-- COMP_TAG_END ------ End COMPONENT Declaration ------------

	------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
	component my_fifo_2
		port (
		CLK: IN std_logic;
		D: IN std_logic_VECTOR(8 downto 0); --(7 downto 0);
		Q: OUT std_logic_VECTOR(8 downto 0); --(7 downto 0);
		CE: IN std_logic);
	end component;

	-- Synplicity black box declaration
	attribute syn_black_box : boolean;
	attribute syn_black_box of my_fifo_2: component is true;

	-- COMP_TAG_END ------ End COMPONENT Declaration ------------



	component port_bus_1to0_1 generic( corr_res_w:integer);
		port(
		clk: in std_logic;
		vidin_addr_reg: out std_logic_vector(18 downto 0);
		svid_comp_switch : out std_logic;
		vidin_new_data_scld_1_1to0: out std_logic;
		v_corr_20: out type_array_8_20;
		vidin_new_data_scld_2_1to0: out std_logic;
		v_corr_10: out type_array_8_10;
		vidin_new_data_scld_4_1to0: out std_logic;
		v_corr_05: out type_array_8_5;
		bus_word_1: in std_logic_vector(7 downto 0);
		bus_word_2: in std_logic_vector(7 downto 0);
		bus_word_3: in std_logic_vector(7 downto 0);
		bus_word_4: in std_logic_vector(7 downto 0);
		bus_word_5: in std_logic_vector(7 downto 0);
		bus_word_6: in std_logic_vector(7 downto 0);
		counter_out: in std_logic_vector(2 downto 0));
	end component;

begin

-------------------------------------------------------------------------------
--------------------   Delay Line for alignment in the   ----------------------
----------------------   first atage after scaler   ---------------------------
-------------------------------------------------------------------------------

	scaler_inst_left: scaler port map(tm3_clk_v0,
					vidin_new_data_fifo,
					vidin_rgb_reg_fifo_left,
					vidin_addr_reg_2to0,
					v_nd_s1_left_2to0_tmp,     
					v_nd_s2_left_2to0_tmp,
					v_nd_s4_left_2to0_tmp,
					v_d_reg_s1_left_2to0_tmp,    
					v_d_reg_s2_left_2to0_tmp,
					v_d_reg_s4_left_2to0_tmp);

	scaler_inst_right: scaler port map(tm3_clk_v0,
					vidin_new_data_fifo,
					vidin_rgb_reg_fifo_right,
					vidin_addr_reg_2to0,
					v_nd_s1_right_2to0_tmp,  	
					v_nd_s2_right_2to0_tmp,
					v_nd_s4_right_2to0_tmp,