sv_chip3.vhd

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

			when "0111101" =>
				tm3_vidin_sda <= iicdata(5);
				tm3_vidin_scl <= '0';
			when "0111110" =>
				tm3_vidin_sda <= iicdata(4);
				tm3_vidin_scl <= '0';
			when "0111111" =>
				tm3_vidin_sda <= iicdata(4);
				tm3_vidin_scl <= '1';
			when "1000000" =>
				tm3_vidin_sda <= iicdata(4);
				tm3_vidin_scl <= '0';
			when "1000001" =>
				tm3_vidin_sda <= iicdata(3);
				tm3_vidin_scl <= '0';
			when "1000010" =>
				tm3_vidin_sda <= iicdata(3);
				tm3_vidin_scl <= '1';
			when "1000011" =>
				tm3_vidin_sda <= iicdata(3);
				tm3_vidin_scl <= '0';
			when "1000100" =>
				tm3_vidin_sda <= iicdata(2);
				tm3_vidin_scl <= '0';
			when "1000101" =>
				tm3_vidin_sda <= iicdata(2);
				tm3_vidin_scl <= '1';
			when "1000110" =>
				tm3_vidin_sda <= iicdata(2);
				tm3_vidin_scl <= '0';
			when "1000111" =>
				tm3_vidin_sda <= iicdata(1);
				tm3_vidin_scl <= '0';
			when "1001000" =>
				tm3_vidin_sda <= iicdata(1);
				tm3_vidin_scl <= '1';
			when "1001001" =>
				tm3_vidin_sda <= iicdata(1);
				tm3_vidin_scl <= '0';
			when "1001010" =>
				tm3_vidin_sda <= iicdata(0);
				tm3_vidin_scl <= '0';
			when "1001011" =>
				tm3_vidin_sda <= iicdata(0);
				tm3_vidin_scl <= '1';
			when "1001100" =>
				tm3_vidin_sda <= iicdata(0);
				tm3_vidin_scl <= '0';
			when "1001101" =>
				tm3_vidin_sda <= '0';
				tm3_vidin_scl <= '0';

			when "1001110" =>
				tm3_vidin_sda <= '0'; -- ack
				tm3_vidin_scl <= '1'; 
			when "1001111" =>
				tm3_vidin_sda <= '0';
				tm3_vidin_scl <= '0';

			when "1010000" =>
				tm3_vidin_sda <= '0';
				tm3_vidin_scl <= '1';
			when "1010001" =>
				iic_stop <= '1';
				tm3_vidin_sda <= '1'; -- stop
				tm3_vidin_scl <= '1';

			when others =>
				iic_stop <= '1';
				tm3_vidin_sda <= '1';
				tm3_vidin_scl <= '1';
		end case;
	end if;
	end process;

	process(reg_prog_state,iic_stop) begin
		rst_done <= '0';
		case(reg_prog_state) is
			when reg_prog1 =>
				rst_done <= '1';
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog2;
				else
					reg_prog_nextstate <= reg_prog1;
				end if;
			
			when reg_prog2 =>
				iicaddr <= "00000010"; -- subaddr 02
				iicdata <= "11000" & "00" & svid_comp_state(0);
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog3;
				else
					reg_prog_nextstate <= reg_prog2;
				end if;
			when reg_prog3 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog4;
				else
					reg_prog_nextstate <= reg_prog3;
				end if;
			when reg_prog4 =>
				iicaddr <= "00000011"; -- subaddr 03
				iicdata <= "00100011"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog5;
				else
					reg_prog_nextstate <= reg_prog4;
				end if;
			when reg_prog5 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog6;
				else
					reg_prog_nextstate <= reg_prog5;
				end if;
			when reg_prog6 =>
				iicaddr <= "00000110"; -- subaddr 06
				iicdata <= "11101011"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog7;
				else
					reg_prog_nextstate <= reg_prog6;
				end if;
			when reg_prog7 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog8;
				else
					reg_prog_nextstate <= reg_prog7;
				end if;
			when reg_prog8 =>
				iicaddr <= "00000111"; -- subaddr 07
				iicdata <= "11100000"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog9;
				else
					reg_prog_nextstate <= reg_prog8;
				end if;
			when reg_prog9 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog10;
				else
					reg_prog_nextstate <= reg_prog9;
				end if;
			when reg_prog10 =>
				iicaddr <= "00001000"; -- subaddr 08
				iicdata <= "10000000"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog11;
				else
					reg_prog_nextstate <= reg_prog10;
				end if;
			when reg_prog11 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog12;
				else
					reg_prog_nextstate <= reg_prog11;
				end if;
			when reg_prog12 =>
				iicaddr <= "00001001"; -- subaddr 09
				iicdata <= "00000001"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog13;
				else
					reg_prog_nextstate <= reg_prog12;
				end if;
			when reg_prog13 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog14;
				else
					reg_prog_nextstate <= reg_prog13;
				end if;
			when reg_prog14 =>
				iicaddr <= "00001010"; -- subaddr 0a
				iicdata <= "10000000"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog15;
				else
					reg_prog_nextstate <= reg_prog14;
				end if;
			when reg_prog15 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog16;
				else
					reg_prog_nextstate <= reg_prog15;
				end if;
			when reg_prog16 =>
				iicaddr <= "00001011"; -- subaddr 0b
				iicdata <= "01000111"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog17;
				else
					reg_prog_nextstate <= reg_prog16;
				end if;
			when reg_prog17 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog18;
				else
					reg_prog_nextstate <= reg_prog17;
				end if;
			when reg_prog18 =>
				iicaddr <= "00001100"; -- subaddr 0c
				iicdata <= "01000000"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog19;
				else
					reg_prog_nextstate <= reg_prog18;
				end if;
			when reg_prog19 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog20;
				else
					reg_prog_nextstate <= reg_prog19;
				end if;
			when reg_prog20 =>
				iicaddr <= "00001110"; -- subaddr 0e
				iicdata <= "00000001"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog21;
				else
					reg_prog_nextstate <= reg_prog20;
				end if;
			when reg_prog21 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog22;
				else
					reg_prog_nextstate <= reg_prog21;
				end if;
			when reg_prog22 =>
				iicaddr <= "00010000"; -- subaddr 10
				iicdata <= "00000000"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog23;
				else
					reg_prog_nextstate <= reg_prog22;
				end if;
			when reg_prog23 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog24;
				else
					reg_prog_nextstate <= reg_prog23;
				end if;
			when reg_prog24 =>
				iicaddr <= "00010001"; -- subaddr 11
				iicdata <= "00011100"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog25;
				else
					reg_prog_nextstate <= reg_prog24;
				end if;
			when reg_prog25 =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '1';
				if iic_stop = '0' then
					reg_prog_nextstate <= reg_prog26;
				else
					reg_prog_nextstate <= reg_prog25;
				end if;
			when reg_prog26 =>
				iicaddr <= "00010010"; -- subaddr 12
				iicdata <= "00001001"; 
				iic_start <= '0';
				if iic_stop = '1' then
					reg_prog_nextstate <= reg_prog_end;
				else
					reg_prog_nextstate <= reg_prog26;
				end if;
			when reg_prog_end =>
				iicaddr <= "00000000";
				iicdata <= "00000000"; 
				iic_start <= '0';
				reg_prog_nextstate <= reg_prog_end;
		end case;
	end process;
			

	process(tm3_clk_v2) begin
		if (tm3_clk_v2'event and tm3_clk_v2 = '1') then
			if rst_done = '1' then
				rst <= '1';
			end if;
			
			temp_reg1 <= tm3_vidin_rts0;
			temp_reg2 <= temp_reg1;
			
			if rst = '0' then
				reg_prog_state <= reg_prog1;
			elsif (temp_reg1 = '0') and (temp_reg2 = '1') then
				reg_prog_state <= reg_prog1;
				svid_comp_state <= not(svid_comp_state);
				svid_comp_switch <= svid_comp_state(2) ;
			else	 
				reg_prog_state <= reg_prog_nextstate;
			end if;
			if iic_stop = '0' then
				iic_state <= iic_state + 1;
			elsif iic_start = '1' then
				iic_state <= "0000001";
			end if;
		end if;
	end process;

end arch_sv_chip3;