408b37b9db26001b1091ad0065de6612

一个在全国电子设计大赛上的基于DE II的实际工程

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * D:\4\DE2Project_restored\software\MY4_syslib\..\..\niosII.ptf
 *
 * Generated: 2006-08-08 19:25:21.625
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "niosII"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00800020
#define NIOS2_RESET_ADDR 0x00140800

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PLL
#define __XIANKA4
#define __ALTERA_AVALON_PIO

/*
 * ext_ram_bus configuration
 *
 */

#define EXT_RAM_BUS_NAME "/dev/ext_ram_bus"
#define EXT_RAM_BUS_TYPE "altera_avalon_tri_state_bridge"

/*
 * ext_flash configuration
 *
 */

#define EXT_FLASH_NAME "/dev/ext_flash"
#define EXT_FLASH_TYPE "altera_avalon_cfi_flash"
#define EXT_FLASH_BASE 0x00000000
#define EXT_FLASH_SPAN 1048576
#define EXT_FLASH_SETUP_VALUE 40
#define EXT_FLASH_WAIT_VALUE 160
#define EXT_FLASH_HOLD_VALUE 40
#define EXT_FLASH_TIMING_UNITS "ns"
#define EXT_FLASH_UNIT_MULTIPLIER 1
#define EXT_FLASH_SIZE 1048576
#define EXT_FLASH_CONTENTS_INFO "SIMDIR/ext_flash.dat 1145005238"

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x00140800
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 0
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 0
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-006"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_CONTENTS_INFO "SIMDIR/epcs_controller_boot_rom.hex 1145005242 SIMDIR/epcs_controller_boot_rom.dat 1145005242"
#define EPCS_CONTROLLER_DELAYUNIT "us"

/*
 * sys_clk_timer configuration
 *
 */

#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
#define SYS_CLK_TIMER_BASE 0x00141000
#define SYS_CLK_TIMER_SPAN 32
#define SYS_CLK_TIMER_IRQ 1
#define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_SNAPSHOT 1
#define SYS_CLK_TIMER_PERIOD 1
#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLK_TIMER_RESET_OUTPUT 0
#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLK_TIMER_MULT 0.001
#define SYS_CLK_TIMER_FREQ 50000000

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x001410D0
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 2
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 0
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0

/*
 * high_res_timer configuration
 *
 */

#define HIGH_RES_TIMER_NAME "/dev/high_res_timer"
#define HIGH_RES_TIMER_TYPE "altera_avalon_timer"
#define HIGH_RES_TIMER_BASE 0x00141020
#define HIGH_RES_TIMER_SPAN 32
#define HIGH_RES_TIMER_IRQ 3
#define HIGH_RES_TIMER_ALWAYS_RUN 0
#define HIGH_RES_TIMER_FIXED_PERIOD 0
#define HIGH_RES_TIMER_SNAPSHOT 1
#define HIGH_RES_TIMER_PERIOD 1
#define HIGH_RES_TIMER_PERIOD_UNITS "us"
#define HIGH_RES_TIMER_RESET_OUTPUT 0
#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define HIGH_RES_TIMER_MULT 0.000001
#define HIGH_RES_TIMER_FREQ 50000000

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x001410D8
#define SYSID_SPAN 8
#define SYSID_ID 1171947352u
#define SYSID_TIMESTAMP 1154916340u

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x00800000
#define SDRAM_SPAN 8388608
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70
#define SDRAM_T_RP 20
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0
#define SDRAM_SHARED_DATA 0
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_CONTENTS_INFO "SIMDIR/sdram.dat 1145005262"

/*
 * pll configuration
 *
 */

#define PLL_NAME "/dev/pll"
#define PLL_TYPE "altera_avalon_pll"
#define PLL_BASE 0x00141060
#define PLL_SPAN 32
#define PLL_LOCKED "None"
#define PLL_ARESET "None"
#define PLL_PLLENA "None"
#define PLL_PFDENA "None"
#define PLL_CONFIG_DONE 1

/*
 * VGA_0 configuration
 *
 */

#define VGA_0_NAME "/dev/VGA_0"
#define VGA_0_TYPE "xianka4"
#define VGA_0_BASE 0x00100000
#define VGA_0_SPAN 262144

/*
 * RGB_DATA configuration
 *
 */

#define RGB_DATA_NAME "/dev/RGB_DATA"
#define RGB_DATA_TYPE "altera_avalon_pio"
#define RGB_DATA_BASE 0x00141080
#define RGB_DATA_SPAN 16
#define RGB_DATA_DO_TEST_BENCH_WIRING 0
#define RGB_DATA_DRIVEN_SIM_VALUE 0x0000
#define RGB_DATA_HAS_TRI 0
#define RGB_DATA_HAS_OUT 0
#define RGB_DATA_HAS_IN 1
#define RGB_DATA_CAPTURE 0
#define RGB_DATA_EDGE_TYPE "NONE"
#define RGB_DATA_IRQ_TYPE "NONE"
#define RGB_DATA_FREQ 50000000

/*
 * LOCK_PIXEL_NUM configuration
 *
 */

#define LOCK_PIXEL_NUM_NAME "/dev/LOCK_PIXEL_NUM"
#define LOCK_PIXEL_NUM_TYPE "altera_avalon_pio"
#define LOCK_PIXEL_NUM_BASE 0x00141090
#define LOCK_PIXEL_NUM_SPAN 16
#define LOCK_PIXEL_NUM_DO_TEST_BENCH_WIRING 0
#define LOCK_PIXEL_NUM_DRIVEN_SIM_VALUE 0x0000
#define LOCK_PIXEL_NUM_HAS_TRI 0
#define LOCK_PIXEL_NUM_HAS_OUT 1
#define LOCK_PIXEL_NUM_HAS_IN 0
#define LOCK_PIXEL_NUM_CAPTURE 0
#define LOCK_PIXEL_NUM_EDGE_TYPE "NONE"
#define LOCK_PIXEL_NUM_IRQ_TYPE "NONE"
#define LOCK_PIXEL_NUM_FREQ 50000000

/*
 * PIXEL_LOCK_LIE configuration
 *
 */

#define PIXEL_LOCK_LIE_NAME "/dev/PIXEL_LOCK_LIE"
#define PIXEL_LOCK_LIE_TYPE "altera_avalon_pio"
#define PIXEL_LOCK_LIE_BASE 0x001410A0
#define PIXEL_LOCK_LIE_SPAN 16
#define PIXEL_LOCK_LIE_DO_TEST_BENCH_WIRING 0
#define PIXEL_LOCK_LIE_DRIVEN_SIM_VALUE 0x0000
#define PIXEL_LOCK_LIE_HAS_TRI 0
#define PIXEL_LOCK_LIE_HAS_OUT 1
#define PIXEL_LOCK_LIE_HAS_IN 0
#define PIXEL_LOCK_LIE_CAPTURE 0
#define PIXEL_LOCK_LIE_EDGE_TYPE "NONE"
#define PIXEL_LOCK_LIE_IRQ_TYPE "NONE"
#define PIXEL_LOCK_LIE_FREQ 50000000

/*
 * whichout configuration
 *
 */

#define WHICHOUT_NAME "/dev/whichout"
#define WHICHOUT_TYPE "altera_avalon_pio"
#define WHICHOUT_BASE 0x001410C0
#define WHICHOUT_SPAN 16
#define WHICHOUT_DO_TEST_BENCH_WIRING 0
#define WHICHOUT_DRIVEN_SIM_VALUE 0x0000
#define WHICHOUT_HAS_TRI 0
#define WHICHOUT_HAS_OUT 1
#define WHICHOUT_HAS_IN 0
#define WHICHOUT_CAPTURE 0
#define WHICHOUT_EDGE_TYPE "NONE"
#define WHICHOUT_IRQ_TYPE "NONE"
#define WHICHOUT_FREQ 50000000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK SYS_CLK_TIMER
#define ALT_TIMESTAMP_CLK HIGH_RES_TIMER

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      EPCS_CONTROLLER


#endif /* __SYSTEM_H_ */