📄 mux8.rpt
字号:
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - C -- OUTPUT 0 1 0 0 q0
69 - - A -- OUTPUT 0 1 0 0 q1
73 - - A -- OUTPUT 0 1 0 0 q2
67 - - B -- OUTPUT 0 1 0 0 q3
61 - - C -- OUTPUT 0 1 0 0 sel0
53 - - - 20 OUTPUT 0 1 0 0 sel1
52 - - - 19 OUTPUT 0 1 0 0 sel2
59 - - C -- OUTPUT 0 1 0 0 sel3
79 - - - 24 OUTPUT 0 1 0 0 sel4
78 - - - 24 OUTPUT 0 1 0 0 sel5
58 - - C -- OUTPUT 0 1 0 0 sel6
60 - - C -- OUTPUT 0 1 0 0 sel7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\mux8.rpt
mux8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 20 DFFE + 0 2 0 8 state2 (:42)
- 2 - C 20 DFFE + 0 1 0 9 state1 (:43)
- 4 - C 23 DFFE + 0 0 0 10 state0 (:44)
- 6 - C 20 OR2 ! 0 3 1 4 :450
- 1 - C 23 OR2 ! 0 3 1 4 :460
- 3 - B 18 OR2 s 2 1 0 1 ~463~1
- 6 - C 23 OR2 ! 0 3 1 4 :470
- 5 - B 18 OR2 1 3 0 1 :473
- 8 - C 20 OR2 ! 0 3 1 4 :480
- 5 - C 20 OR2 ! 0 3 1 4 :490
- 6 - B 18 OR2 1 3 0 1 :493
- 7 - C 20 OR2 ! 0 3 1 4 :500
- 7 - B 18 OR2 1 2 0 1 :503
- 3 - C 20 OR2 ! 0 3 1 4 :510
- 1 - B 18 OR2 1 2 1 0 :513
- 2 - B 18 OR2 2 1 0 1 :519
- 4 - B 18 OR2 1 3 0 1 :525
- 6 - A 15 OR2 1 2 0 1 :528
- 7 - A 15 OR2 1 3 0 1 :534
- 1 - A 15 OR2 1 2 1 0 :537
- 2 - A 15 OR2 s 2 1 0 1 ~546~1
- 3 - A 15 OR2 1 3 0 1 :549
- 4 - A 15 OR2 1 3 0 1 :555
- 5 - A 15 OR2 1 2 0 1 :558
- 8 - A 15 OR2 1 2 1 0 :561
- 2 - C 23 OR2 2 1 0 1 :567
- 5 - C 23 OR2 1 3 0 1 :573
- 7 - C 23 OR2 1 2 0 1 :576
- 8 - C 23 OR2 1 3 0 1 :582
- 3 - C 23 OR2 1 2 1 0 :585
- 4 - C 20 AND2 0 3 1 0 :611
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\mux8.rpt
mux8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 11/ 48( 22%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
B: 9/ 96( 9%) 0/ 48( 0%) 8/ 48( 16%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 9/ 48( 18%) 1/16( 6%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\mux8.rpt
mux8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\mux8.rpt
mux8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
clk : INPUT;
c0 : INPUT;
c1 : INPUT;
c2 : INPUT;
c3 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
e0 : INPUT;
e1 : INPUT;
e2 : INPUT;
e3 : INPUT;
f0 : INPUT;
f1 : INPUT;
f2 : INPUT;
f3 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC3_C23;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC8_A15;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC1_A15;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC1_B18;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC3_C20;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC7_C20;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC5_C20;
-- Node name is 'sel3'
-- Equation name is 'sel3', type is output
sel3 = _LC8_C20;
-- Node name is 'sel4'
-- Equation name is 'sel4', type is output
sel4 = _LC6_C23;
-- Node name is 'sel5'
-- Equation name is 'sel5', type is output
sel5 = _LC1_C23;
-- Node name is 'sel6'
-- Equation name is 'sel6', type is output
sel6 = _LC6_C20;
-- Node name is 'sel7'
-- Equation name is 'sel7', type is output
sel7 = _LC4_C20;
-- Node name is ':44' = 'state0'
-- Equation name is 'state0', location is LC4_C23, type is buried.
state0 = DFFE(!state0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':43' = 'state1'
-- Equation name is 'state1', location is LC2_C20, type is buried.
state1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = state0 & !state1
# !state0 & state1;
-- Node name is ':42' = 'state2'
-- Equation name is 'state2', location is LC1_C20, type is buried.
state2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !state0 & state2
# !state1 & state2
# state0 & state1 & !state2;
-- Node name is ':450'
-- Equation name is '_LC6_C20', type is buried
!_LC6_C20 = _LC6_C20~NOT;
_LC6_C20~NOT = LCELL( _EQ003);
_EQ003 = state0
# !state1
# !state2;
-- Node name is ':460'
-- Equation name is '_LC1_C23', type is buried
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL( _EQ004);
_EQ004 = !state0
# state1
# !state2;
-- Node name is '~463~1'
-- Equation name is '~463~1', location is LC3_B18, type is buried.
-- synthesized logic cell
_LC3_B18 = LCELL( _EQ005);
_EQ005 = a3 & !_LC6_C20
# b3 & _LC6_C20;
-- Node name is ':470'
-- Equation name is '_LC6_C23', type is buried
!_LC6_C23 = _LC6_C23~NOT;
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