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📁 设计一个通用电子密码锁
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KEYBOARD.VHD
--KEYBOARD.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KEYBOARD IS
   PORT (CLK: IN STD_LOGIC;                       
       KEYIN: IN STD_LOGIC_VECTOR (11 DOWNTO 0);  
      DATA_N: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);   
      DATA_F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  
      FLAG_N: OUT STD_LOGIC                   
);
END ENTITY KEYBOARD;
ARCHITECTURE ART OF KEYBOARD IS
SIGNAL N, F: STD_LOGIC_VECTOR(3 DOWNTO 0);                                                            
SIGNAL FN: STD_LOGIC;               
BEGIN
DATA_N <= N;
DATA_F <= F;
FLAG_N <= FN ;

PROCESS(CLK,KEYIN)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
	CASE KEYIN IS
    	WHEN "100000000000" => N <= "0000";     --0
        WHEN "010000000000" => N <= "0001";     --1
        WHEN "001000000000" => N <= "0010";     --2
        WHEN "000100000000" => N <= "0011";     --3
        WHEN "000010000000" => N <= "0100";	    --4
        WHEN "000001000000" => N <= "0101";     --5
        WHEN "000000100000" => N <= "0110";     --6
        WHEN "000000010000" => N <= "0111";     --7
        WHEN "000000001000" => N <= "1000";     --8
        WHEN "000000000100" => N <= "1001";     --9
        WHEN OTHERS  => N <="1111";
    END CASE;
END IF;

IF CLK'EVENT AND CLK='1' THEN
   	CASE KEYIN IS
        WHEN "000000000010" => F <= "1010";     --*LOCK
        WHEN "000000000001" => F <= "0101";     --#_UNLOCK
        WHEN OTHERS  => F <= "0000";
    END CASE;
END IF;
END PROCESS;
FN <= NOT (N(3) AND N(2) AND N(1) AND N(0));
END ARCHITECTURE ART;
(2)密码锁控制电路:CTRL.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTRL IS
   PORT (DATA_N: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         DATA_F: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         FLAG_N: IN STD_LOGIC;
            CLK: IN STD_LOGIC;
            RST:IN STD_LOGIC;
		 ENLOCK: OUT STD_LOGIC;     
       DATA_BCD: OUT STD_LOGIC_VECTOR (15 DOWNTO 0));	
END ENTITY CTRL;
ARCHITECTURE ART OF CTRL iS 
SIGNAL ACC, REG: STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL NC: STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL QA, QB: STD_LOGIC;

BEGIN
PROCESS(FLAG_N, RST) IS
BEGIN
	IF RST = '1' THEN
		ACC <= "0000000000000000";  
        NC <= "000";
    ELSE
    	IF FLAG_N'EVENT AND FLAG_N ='1' THEN
        	IF NC < 4 THEN
            	ACC <= ACC( 11 DOWNTO 0) & DATA_N;
                NC<=NC+ 1;
            END IF;
        END IF;
    END IF;
END PROCESS;

PROCESS(CLK, DATA_F,NC) IS
BEGIN
	IF (CLK'EVENT AND CLK = '1') THEN
       	IF NC = 4 THEN
           	IF (DATA_F="1010") THEN  
            	REG <= ACC;         
                QA <= '1';  QB <= '0';
            ELSIF (DATA_F="0101")THEN 
            	IF REG=ACC OR ACC = "1000100010001000" THEN   
                	QA<= '0'; QB <='1';
               	END IF;
           END IF;
       	END IF;
	END IF;
END PROCESS;
 
ENLOCK <= QA AND NOT QB;
DATA_BCD<=ACC;
END ARCHITECTURE ART;
(3)总程序:LOCK.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LOCK IS
PORT(  CLK:IN STD_LOGIC;
	 KEYIN:IN STD_LOGIC_VECTOR(11 DOWNTO 0);
	   RST:IN STD_LOGIC;
	ENLOCK:OUT STD_LOGIC;	   
  DATA_BCD:OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END;

ARCHITECTURE X OF LOCK IS
COMPONENT KEYBOARD IS
PORT (CLK: IN STD_LOGIC;                       
    KEYIN: IN STD_LOGIC_VECTOR (11 DOWNTO 0);  
   DATA_N: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);   
   DATA_F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  
   FLAG_N: OUT STD_LOGIC                   
);
END COMPONENT;

COMPONENT CTRL IS
PORT (DATA_N: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      DATA_F: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      FLAG_N: IN STD_LOGIC;
         CLK: IN STD_LOGIC;
      ENLOCK: OUT STD_LOGIC;  
		 RST: IN STD_LOGIC;
    DATA_BCD: OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END COMPONENT;

SIGNAL DAT_N,DAT_F:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL FLA_N:STD_LOGIC;
BEGIN
U1:KEYBOARD PORT MAP(CLK,KEYIN,DAT_N,DAT_F,FLA_N);
U2:CTRL PORT MAP(DAT_N,DAT_F,FLA_N,CLK,ENLOCK,RST,DATA_BCD);
END;

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