cagenerator.vhd

GPS对应的CA短码发生电路的VHDL描述程序

--************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--**********************
entity CAGenerator is
port(
	CLKIN:IN STD_LOGIC;
	X1IN:IN STD_LOGIC;
	SWITCH:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
	CAOUT:OUT STD_LOGIC;
	CLK50:OUT STD_LOGIC
	);
end CAGenerator;
--***********************
architecture a of CAGenerator is
signal G1,G2:std_logic_vector(9 downto 0);
signal CLKCOUNT_FOR20DIVIDE:std_logic_vector(4 downto 0);
signal CLKCOUNT_FOR10DIVIDE:std_logic_vector(3 downto 0);
signal test:std_logic_vector(5 downto 0);
signal CLK,CLKTMP,CLK50TMP,G1OUT,G2OUT:std_logic;
begin
	--******************************
	--10.23MHz divide to 1.023MHz
	CLKGenerator:process(CLKIN,X1IN)
	begin
		if X1IN='1' then
			CLKCOUNT_FOR10DIVIDE<="0000";clk<='0';
		elsif clkin'event and clkin='0' then
			if CLKCOUNT_FOR10DIVIDE=9 then
				CLKCOUNT_FOR10DIVIDE<="0000";
				CLK<='1';
			else
				CLKCOUNT_FOR10DIVIDE<=CLKCOUNT_FOR10DIVIDE+1;
				CLK<='0';
			end if;
		end if;
	end process CLKGenerator;
		
	--******************************
	--G1Generator
	G1Generator:process(clk,X1IN)
	begin
		if X1IN='1' then
			G1<="1111111111";
		elsif clk'event and clk='1' then
			for i in 1 to 9 loop
				G1(i)<=G1(i-1);
			end loop;
			G1(0)<=G1(2) xor G1(9);
		end if;
	end process G1Generator;
	G1OUT<=G1(9);
	--*******************************
	--G2 and 1KHz clock Generator
	G2Generator:process(clk,X1IN)
	begin
		if X1IN='1' then
			G2<="1111111111";
		elsif clk'event and clk='1' then
			for j in 1 to 9 loop
				G2(j)<=G2(j-1);
			end loop;
			G2(0)<=G2(1) xor G2(2) xor G2(5) xor G2(7) xor G2(8) xor G2(9);
		end if;
		
		if G2="0111111111" then 
			clktmp<='1';
		else 
			clktmp<='0';
		end if;
	end process G2Generator;
	--*******************************
	--1KHz divide to 50Hz
	CLK50Generator:process(X1IN,clktmp)
	begin
		if X1IN='1' then
			CLKCOUNT_FOR20DIVIDE<="00000";CLK50TMP<='0';
		elsif clktmp'event and clktmp='1' then
			if CLKCOUNT_FOR20DIVIDE=19 then
				CLKCOUNT_FOR20DIVIDE<="00000";
				CLK50TMP<='1';
			else
				CLKCOUNT_FOR20DIVIDE<=CLKCOUNT_FOR20DIVIDE+1;
				CLK50TMP<='0';
			end if;
		end if;
	end process CLK50Generator;
	CLK50<=CLK50TMP;
	--********************************
	--Choose ports for final G2 siganl
	G2PortSelect:block
	begin
		with SWITCH select G2OUT<=
			G2(1) xor G2(5) when "000000", --00000 for#1
			G2(2) xor G2(6) when "000001",
			G2(3) xor G2(7) when "000010",
			G2(4) xor G2(8) when "000011",
			G2(0) xor G2(8) when "000100",
			G2(1) xor G2(5) when "000101",
			G2(0) xor G2(7) when "000110",
			G2(1) xor G2(8) when "000111",
			G2(2) xor G2(9) when "001000",--01000 for #9
			G2(1) xor G2(2) when "001001",
			G2(2) xor G2(3) when "001010",
			G2(4) xor G2(5) when "001011",
			G2(5) xor G2(6) when "001100",
			G2(6) xor G2(7) when "001101",
			G2(7) xor G2(8) when "001110",
			G2(8) xor G2(9) when "001111",
			G2(0) xor G2(3) when "010000",
			G2(1) xor G2(4) when "010001",
			G2(2) xor G2(5) when "010010",--10010 for #19 			
			G2(3) xor G2(6) when "010011",
			G2(4) xor G2(7) when "010100",
			G2(5) xor G2(8) when "010101",
			G2(0) xor G2(2) when "010110",
			G2(3) xor G2(5) when "010111",
			G2(4) xor G2(6) when "011000",
			G2(5) xor G2(7) when "011001",
			G2(6) xor G2(8) when "011010",
			G2(7) xor G2(9) when "011011",
			G2(0) xor G2(5) when "011100",--11100 for #29
			G2(1) xor G2(6) when "011101",
			G2(2) xor G2(7) when "011110",
			G2(3) xor G2(8) when "011111",--11111 for #32 
			G2(4) xor G2(9) when "100000",--#33 to #37 are not satellites
			G2(3) xor G2(9) when "100001",
			G2(0) xor G2(6) when "100010",
			G2(1) xor G2(7) when "100011",
			G2(3) xor G2(9) when "100100",--100100 for #37
			'0' when others;
	end block G2PortSelect;
	--*********************************
	--G1OUT and G2OUT generate CA Code
	CAOUT<=G1OUT xor G2OUT;
	--*********test
	process(X1IN,clk50tmp)
	begin
		if X1IN='1' then 
			test<="000000";
		elsif clk50tmp'event and clk50tmp='1' then
			test<=test+1;
		end if;
	end process;
	
end a;