gp_reg.vhd

Divisor do Tipo com restaura莽茫o sequencial

library divisor ;
use divisor.pkg_divisor.ALL ;

entity gp_reg is
    
   PORT (        a : in bit_vector( ( bit_width - 1) downto 0 );
	         ck,rst : in bit ;
	            ld1 : in bit ;
	            gp4 : out bit  ) ;
	        
end gp_reg;

architecture Behavioral of gp_reg is
signal a_rot_left : bit_vector( ( bit_width - 1) downto 0 ) ;
begin
  
   control : process (ck,rst,ld1)
   variable flag : boolean := false ;   
   begin
       
   if rst = '1' then 

      flag := false;
      a_rot_left <= a;
   
   end if;  
         
   if ( ck'event and ck = '1' ) then 
   
      if ( ld1 = '1' ) then
   
            if ( flag = false ) then 
                a_rot_left <= a rol 1 ;
                flag := true ;
                else 
                   a_rot_left <= a_rot_left rol 1 ;
                   if ( a_rot_left = a ) then 
                      NULL ;
                   end if ;
            end if ;
         
         gp4 <= a_rot_left(4);
      
         end if ;   
      end if;  
      
    
      
    
   
           
   end process control ;              
  
         
        
end Behavioral;