controller.vhd

来自「Divisor do Tipo com restaura莽茫o sequenci」· VHDL 代码 · 共 20 行

entity controller is

    Port (   ck, ctrl : in  bit ;
             ld1, ld2 : out bit ) ;
			  
end controller;

architecture Behavioral of controller is
begin
	

   ld1 <= '1' when ( ctrl = '1' ) else
          '0' ;

   ld2 <= '1' when ( ctrl = '1' ) else
          '0' ;

end Behavioral;