_deps

Modelsim DDR2 SDRAM files

H 2141964 10 4 0 9 9 0 0 0 0
L 6 unisim 21 $MODEL_TECH/../unisim
L 4 ieee 19 $MODEL_TECH/../ieee
L 3 std 18 $MODEL_TECH/../std
L 4 work 4 work
D 65 /export/home/hidalgo/modeltech/linux_x86_64/../unisim.vcomponents 4c`LB>I[`=5V?WL6F==Ha0 0 1
D 27 work.mig_23_addr_gen_0(arc) c5C]O^UcO:5e`eTTJkSCh3 3 1
D 26 work.mig_23_cmd_fsm_0(arc) WhoQHaZ36>>O6Dg==k:XH1 4 1
D 27 work.mig_23_cmp_data_0(arc) eTJo1Kl5L:@ozU6=nd3@c3 5 1
D 27 work.mig_23_data_gen_0(arc) `@jfnDNPH^bz3T:IBJMfh3 6 1
D 24 work.mig_23_parameters_0 l[UAChkPA=3:CB=PU?SDm3 1 1
D 29 work.mig_23_test_bench_0(arc) 6okDEiMbzEiBEW?FJMj_b1 7 1
D 21 work.sim_tb_top(arch) oQbB`Y2T@E[7:dE5a:e>Z3 8 1
D 27 work.wiredelay(wiredelay_a) Y@OKgfK4miJT4YA1j=:830 2 1
2 0  0 L>0PmQcN;6_28[V;CISmW0 2 2 1
2 0  0 gkSZIn8zGdi_JB@2XK8bA1 7 7 1
2 0  0 Y^LKCF@>1M3Y>Pb>;XRIX1 8 8 1
2 0  0 eGLHXhLnHTV4l5nLS^NU]3 0 0 1
2 0  0 8f[lAM]d>aF<;SZo`SkGU3 3 3 1
2 0  0 m9od<LZzR^?09H=4VZHXU2 1 1 1
2 0  0 S_Y;A8j9;nQ7ieH=SkU[?0 6 6 1
2 0  0 NDEMla33^loY1L0N>7G?P0 5 5 1
2 0  0 zMk7?a;5_2zfUeGH@[WMV1 4 4 1