daout.par

正弦波的vhdl输出

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

DDFAB4C28E53470::  Fri Aug 17 21:29:30 2007

par -w -intstyle ise -ol high -t 1 -n 3 daout_map.ncd mppr_result.dir daout.pcf


Constraints file: daout.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "daout" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            16 out of 141    11%
      Number of LOCed IOBs             0 out of 16      0%

   Number of Slices                    2 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   High (set by user)
Placer effort level (-pl):    High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    High (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896b8) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
.
.
.
.
Phase 6.8 (Checksum:9de123) REAL time: 4 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 4 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 4 secs 

Writing design to file mppr_result.dir/H_H_1.ncd


Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 4 secs 

Starting Router

Phase 1: 53 unrouted;       REAL time: 4 secs 

Phase 2: 32 unrouted;       REAL time: 4 secs 

Phase 3: 3 unrouted;       REAL time: 4 secs 

Phase 4: 3 unrouted; (4939)      REAL time: 4 secs 

Phase 5: 3 unrouted; (0)      REAL time: 4 secs 

Phase 6: 0 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 


WARNING:CLK Net:u1/cnnet
may have excessive skew because 2 NON-CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX6| No   |    2 |  0.040     |  1.073      |
+---------------------+--------------+------+------+------------+-------------+
|            u1/cnnet |         Local|      |   17 |  0.254     |  2.874      |
+---------------------+--------------+------+------+------------+-------------+


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.943
   The MAXIMUM PIN DELAY IS:                               2.874
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.452

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           3          16          16           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  86 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file mppr_result.dir/H_H_1.ncd



PAR done!