_primary.vhd

<<精通VerilogHDL IC设计核心技术实例详解>>一书的附录源代码。

library verilog;
use verilog.vl_types.all;
entity comp is
    port(
        a1              : in     vl_logic_vector(3 downto 0);
        a2              : in     vl_logic_vector(3 downto 0);
        min             : out    vl_logic_vector(3 downto 0);
        max             : out    vl_logic_vector(3 downto 0)
    );
end comp;