adc.vhd

2008年北京市大学生电子设计竞赛程序源代码[测频率

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity adc is
 port( clk:             in std_logic;
       INT:             in std_logic;
       data_in:         in std_logic_vector(7 downto 0);
       mode:            out std_logic;
       cs:              out std_logic;
       rd:              out std_logic;
       wr_rdy:          out std_logic;
       data_out:        out std_logic_vector(7 downto 0)
       
             );
end;


architecture behav of adc is

type states is ( st0, st1, st2, st3, st4,st5,st6,st7,st8,st9,st10,st11,st12,st13,st14,st15,st16,st17,st18,st19,st20,st21,st22,st23,st24,st25) ;
signal current_state, next_state: states:= st0;

begin

process( current_state, INT)

begin

case current_state is

when st0 => 
          MODE <= '0'; cs <= '1'; 
          RD <= '1'; next_state <= st1;
   
when st1 =>
          MODE <= '0'; cs <= '0';
          RD <= '1'; next_state <= st2;
          
when st2 =>
         MODE <= '0'; cs <= '0'; RD <= '0';
         if( INT ='1') then next_state <= st2;     
         else
          next_state <=st3;
         end if;
   
when st3 => 
         MODE <= '0'; cs <= '0'; RD <= '0';next_state <= st4;

when st4 =>
         MODE <= '0'; cs <= '0'; RD <= '1';data_out<=data_in;next_state <= st5;

when st5 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st6;
when st6 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st7;
when st7 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st8;
when st8 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st9;
when st9 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st10;
when st10 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st11;
when st11 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st12;
when st12 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st13;
when st13 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st14;
when st14 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st15;
when st15 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st16;
when st16 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st17;
when st17 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st18;
when st18 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st19;
when st19 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st20;
when st20 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st21;
when st21 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st22;
when st22 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st23;
when st23=> 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st24;
when st24 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st25;
when st25 => 
         MODE <= '0'; cs <= '0'; RD <= '1';next_state <= st0;

when others =>
         MODE <= '0'; cs <= '1'; RD <= '1'; next_state <= st0;

end case;

end process;


process( clk)
begin
if ( clk'event and clk = '1') then current_state <= next_state;
end if;
end process;

end;