📄 prev_cmp_ad0820.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register adc:inst\|data_out\[2\] register findmax:inst10\|outbuff\[4\] 34.58 MHz 28.918 ns Internal " "Info: Clock \"clk\" has Internal fmax of 34.58 MHz between source register \"adc:inst\|data_out\[2\]\" and destination register \"findmax:inst10\|outbuff\[4\]\" (period= 28.918 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.409 ns + Longest register register " "Info: + Longest register to register delay is 4.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc:inst\|data_out\[2\] 1 REG LC_X8_Y9_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y9_N5; Fanout = 3; REG Node = 'adc:inst\|data_out\[2\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "" { adc:inst|data_out[2] } "NODE_NAME" } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.276 ns) + CELL(0.564 ns) 1.840 ns findmax:inst10\|outbuff\[2\]~63 2 COMB LC_X7_Y10_N2 1 " "Info: 2: + IC(1.276 ns) + CELL(0.564 ns) = 1.840 ns; Loc. = LC_X7_Y10_N2; Fanout = 1; COMB Node = 'findmax:inst10\|outbuff\[2\]~63'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { adc:inst|data_out[2] findmax:inst10|outbuff[2]~63 } "NODE_NAME" } } { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.918 ns findmax:inst10\|outbuff\[3\]~57 3 COMB LC_X7_Y10_N3 1 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.918 ns; Loc. = LC_X7_Y10_N3; Fanout = 1; COMB Node = 'findmax:inst10\|outbuff\[3\]~57'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { findmax:inst10|outbuff[2]~63 findmax:inst10|outbuff[3]~57 } "NODE_NAME" } } { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.096 ns findmax:inst10\|outbuff\[4\]~49 4 COMB LC_X7_Y10_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 2.096 ns; Loc. = LC_X7_Y10_N4; Fanout = 1; COMB Node = 'findmax:inst10\|outbuff\[4\]~49'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { findmax:inst10|outbuff[3]~57 findmax:inst10|outbuff[4]~49 } "NODE_NAME" } } { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.717 ns findmax:inst10\|LessThan0~33 5 COMB LC_X7_Y10_N8 8 " "Info: 5: + IC(0.000 ns) + CELL(0.621 ns) = 2.717 ns; Loc. = LC_X7_Y10_N8; Fanout = 8; COMB Node = 'findmax:inst10\|LessThan0~33'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { findmax:inst10|outbuff[4]~49 findmax:inst10|LessThan0~33 } "NODE_NAME" } } { "d:/quartersii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartersii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(1.225 ns) 4.409 ns findmax:inst10\|outbuff\[4\] 6 REG LC_X7_Y10_N4 3 " "Info: 6: + IC(0.467 ns) + CELL(1.225 ns) = 4.409 ns; Loc. = LC_X7_Y10_N4; Fanout = 3; REG Node = 'findmax:inst10\|outbuff\[4\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { findmax:inst10|LessThan0~33 findmax:inst10|outbuff[4] } "NODE_NAME" } } { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.666 ns ( 60.47 % ) " "Info: Total cell delay = 2.666 ns ( 60.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.743 ns ( 39.53 % ) " "Info: Total interconnect delay = 1.743 ns ( 39.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "4.409 ns" { adc:inst|data_out[2] findmax:inst10|outbuff[2]~63 findmax:inst10|outbuff[3]~57 findmax:inst10|outbuff[4]~49 findmax:inst10|LessThan0~33 findmax:inst10|outbuff[4] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "4.409 ns" { adc:inst|data_out[2] {} findmax:inst10|outbuff[2]~63 {} findmax:inst10|outbuff[3]~57 {} findmax:inst10|outbuff[4]~49 {} findmax:inst10|LessThan0~33 {} findmax:inst10|outbuff[4] {} } { 0.000ns 1.276ns 0.000ns 0.000ns 0.000ns 0.467ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.621ns 1.225ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.013 ns - Smallest " "Info: - Smallest clock skew is -10.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.768 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_10 67 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 67; CLK Node = 'clk'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0820.bdf" "" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { -144 -248 -80 -128 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns findmax:inst10\|outbuff\[4\] 2 REG LC_X7_Y10_N4 3 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X7_Y10_N4; Fanout = 3; REG Node = 'findmax:inst10\|outbuff\[4\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk findmax:inst10|outbuff[4] } "NODE_NAME" } } { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk findmax:inst10|outbuff[4] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} findmax:inst10|outbuff[4] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.781 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_10 67 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 67; CLK Node = 'clk'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0820.bdf" "" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { -144 -248 -80 -128 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns sinA:inst7\|counter\[0\] 2 REG LC_X9_Y6_N2 31 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X9_Y6_N2; Fanout = 31; REG Node = 'sinA:inst7\|counter\[0\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk sinA:inst7|counter[0] } "NODE_NAME" } } { "sinA.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/sinA.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.858 ns) + CELL(0.935 ns) 7.757 ns adc:inst\|current_state.st4 3 REG LC_X26_Y7_N5 9 " "Info: 3: + IC(3.858 ns) + CELL(0.935 ns) = 7.757 ns; Loc. = LC_X26_Y7_N5; Fanout = 9; REG Node = 'adc:inst\|current_state.st4'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "4.793 ns" { sinA:inst7|counter[0] adc:inst|current_state.st4 } "NODE_NAME" } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.732 ns) + CELL(0.292 ns) 12.781 ns adc:inst\|data_out\[2\] 4 REG LC_X8_Y9_N5 3 " "Info: 4: + IC(4.732 ns) + CELL(0.292 ns) = 12.781 ns; Loc. = LC_X8_Y9_N5; Fanout = 3; REG Node = 'adc:inst\|data_out\[2\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "5.024 ns" { adc:inst|current_state.st4 adc:inst|data_out[2] } "NODE_NAME" } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.631 ns ( 28.41 % ) " "Info: Total cell delay = 3.631 ns ( 28.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.150 ns ( 71.59 % ) " "Info: Total interconnect delay = 9.150 ns ( 71.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "12.781 ns" { clk sinA:inst7|counter[0] adc:inst|current_state.st4 adc:inst|data_out[2] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "12.781 ns" { clk {} clk~out0 {} sinA:inst7|counter[0] {} adc:inst|current_state.st4 {} adc:inst|data_out[2] {} } { 0.000ns 0.000ns 0.560ns 3.858ns 4.732ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk findmax:inst10|outbuff[4] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} findmax:inst10|outbuff[4] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "12.781 ns" { clk sinA:inst7|counter[0] adc:inst|current_state.st4 adc:inst|data_out[2] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "12.781 ns" { clk {} clk~out0 {} sinA:inst7|counter[0] {} adc:inst|current_state.st4 {} adc:inst|data_out[2] {} } { 0.000ns 0.000ns 0.560ns 3.858ns 4.732ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } { "findmax.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/findmax.vhd" 22 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "4.409 ns" { adc:inst|data_out[2] findmax:inst10|outbuff[2]~63 findmax:inst10|outbuff[3]~57 findmax:inst10|outbuff[4]~49 findmax:inst10|LessThan0~33 findmax:inst10|outbuff[4] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "4.409 ns" { adc:inst|data_out[2] {} findmax:inst10|outbuff[2]~63 {} findmax:inst10|outbuff[3]~57 {} findmax:inst10|outbuff[4]~49 {} findmax:inst10|LessThan0~33 {} findmax:inst10|outbuff[4] {} } { 0.000ns 1.276ns 0.000ns 0.000ns 0.000ns 0.467ns } { 0.000ns 0.564ns 0.078ns 0.178ns 0.621ns 1.225ns } "" } } { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk findmax:inst10|outbuff[4] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} findmax:inst10|outbuff[4] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "12.781 ns" { clk sinA:inst7|counter[0] adc:inst|current_state.st4 adc:inst|data_out[2] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "12.781 ns" { clk {} clk~out0 {} sinA:inst7|counter[0] {} adc:inst|current_state.st4 {} adc:inst|data_out[2] {} } { 0.000ns 0.000ns 0.560ns 3.858ns 4.732ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 47 " "Warning: Circuit may not operate. Detected 47 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "df:inst5\|sig_save\[5\] adc:inst\|data_out\[5\] clk 9.167 ns " "Info: Found hold time violation between source pin or register \"df:inst5\|sig_save\[5\]\" and destination pin or register \"adc:inst\|data_out\[5\]\" for clock \"clk\" (Hold time is 9.167 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.020 ns + Largest " "Info: + Largest clock skew is 10.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.788 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_10 67 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 67; CLK Node = 'clk'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0820.bdf" "" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { -144 -248 -80 -128 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns sinA:inst7\|counter\[0\] 2 REG LC_X9_Y6_N2 31 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X9_Y6_N2; Fanout = 31; REG Node = 'sinA:inst7\|counter\[0\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk sinA:inst7|counter[0] } "NODE_NAME" } } { "sinA.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/sinA.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.858 ns) + CELL(0.935 ns) 7.757 ns adc:inst\|current_state.st4 3 REG LC_X26_Y7_N5 9 " "Info: 3: + IC(3.858 ns) + CELL(0.935 ns) = 7.757 ns; Loc. = LC_X26_Y7_N5; Fanout = 9; REG Node = 'adc:inst\|current_state.st4'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "4.793 ns" { sinA:inst7|counter[0] adc:inst|current_state.st4 } "NODE_NAME" } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.739 ns) + CELL(0.292 ns) 12.788 ns adc:inst\|data_out\[5\] 4 REG LC_X8_Y10_N4 3 " "Info: 4: + IC(4.739 ns) + CELL(0.292 ns) = 12.788 ns; Loc. = LC_X8_Y10_N4; Fanout = 3; REG Node = 'adc:inst\|data_out\[5\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "5.031 ns" { adc:inst|current_state.st4 adc:inst|data_out[5] } "NODE_NAME" } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.631 ns ( 28.39 % ) " "Info: Total cell delay = 3.631 ns ( 28.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.157 ns ( 71.61 % ) " "Info: Total interconnect delay = 9.157 ns ( 71.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "12.788 ns" { clk sinA:inst7|counter[0] adc:inst|current_state.st4 adc:inst|data_out[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "12.788 ns" { clk {} clk~out0 {} sinA:inst7|counter[0] {} adc:inst|current_state.st4 {} adc:inst|data_out[5] {} } { 0.000ns 0.000ns 0.560ns 3.858ns 4.739ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.768 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_10 67 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 67; CLK Node = 'clk'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0820.bdf" "" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { -144 -248 -80 -128 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns df:inst5\|sig_save\[5\] 2 REG LC_X8_Y10_N0 1 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y10_N0; Fanout = 1; REG Node = 'df:inst5\|sig_save\[5\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk df:inst5|sig_save[5] } "NODE_NAME" } } { "df.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/df.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk df:inst5|sig_save[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} df:inst5|sig_save[5] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "12.788 ns" { clk sinA:inst7|counter[0] adc:inst|current_state.st4 adc:inst|data_out[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "12.788 ns" { clk {} clk~out0 {} sinA:inst7|counter[0] {} adc:inst|current_state.st4 {} adc:inst|data_out[5] {} } { 0.000ns 0.000ns 0.560ns 3.858ns 4.739ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns } "" } } { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk df:inst5|sig_save[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} df:inst5|sig_save[5] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "df.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/df.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.629 ns - Shortest register register " "Info: - Shortest register to register delay is 0.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns df:inst5\|sig_save\[5\] 1 REG LC_X8_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N0; Fanout = 1; REG Node = 'df:inst5\|sig_save\[5\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "" { df:inst5|sig_save[5] } "NODE_NAME" } } { "df.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/df.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.114 ns) 0.629 ns adc:inst\|data_out\[5\] 2 REG LC_X8_Y10_N4 3 " "Info: 2: + IC(0.515 ns) + CELL(0.114 ns) = 0.629 ns; Loc. = LC_X8_Y10_N4; Fanout = 3; REG Node = 'adc:inst\|data_out\[5\]'" { } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "0.629 ns" { df:inst5|sig_save[5] adc:inst|data_out[5] } "NODE_NAME" } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.114 ns ( 18.12 % ) " "Info: Total cell delay = 0.114 ns ( 18.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.515 ns ( 81.88 % ) " "Info: Total interconnect delay = 0.515 ns ( 81.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "0.629 ns" { df:inst5|sig_save[5] adc:inst|data_out[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "0.629 ns" { df:inst5|sig_save[5] {} adc:inst|data_out[5] {} } { 0.000ns 0.515ns } { 0.000ns 0.114ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "df.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/df.vhd" 20 -1 0 } } { "adc.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adc.vhd" 26 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "12.788 ns" { clk sinA:inst7|counter[0] adc:inst|current_state.st4 adc:inst|data_out[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "12.788 ns" { clk {} clk~out0 {} sinA:inst7|counter[0] {} adc:inst|current_state.st4 {} adc:inst|data_out[5] {} } { 0.000ns 0.000ns 0.560ns 3.858ns 4.739ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns } "" } } { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk df:inst5|sig_save[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~out0 {} df:inst5|sig_save[5] {} } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartersii/quartus/bin/TimingClosureFloorplan.fld" "" "0.629 ns" { df:inst5|sig_save[5] adc:inst|data_out[5] } "NODE_NAME" } } { "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartersii/quartus/bin/Technology_Viewer.qrui" "0.629 ns" { df:inst5|sig_save[5] {} adc:inst|data_out[5] {} } { 0.000ns 0.515ns } { 0.000ns 0.114ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -