prev_cmp_ad0820.qmsg

2008年北京市大学生电子设计竞赛程序源代码[测频率

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Vtab Vtab:inst1 " "Info: Elaborating entity \"Vtab\" for hierarchy \"Vtab:inst1\"" {  } { { "ad0820.bdf" "inst1" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { 16 408 568 144 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "addbcd.vhd 2 1 " "Warning: Using design file addbcd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addbcd-a1 " "Info: Found design unit 1: addbcd-a1" {  } { { "addbcd.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/addbcd.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 addbcd " "Info: Found entity 1: addbcd" {  } { { "addbcd.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/addbcd.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addbcd Vtab:inst1\|addbcd:ad1 " "Info: Elaborating entity \"addbcd\" for hierarchy \"Vtab:inst1\|addbcd:ad1\"" {  } { { "Vtab.vhd" "ad1" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/Vtab.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "a addbcd.vhd(18) " "Warning (10036): Verilog HDL or VHDL warning at addbcd.vhd(18): object \"a\" assigned a value but never read" {  } { { "addbcd.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/addbcd.vhd" 18 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "adder.vhd 2 1 " "Warning: Using design file adder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder-a " "Info: Found design unit 1: adder-a" {  } { { "adder.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adder.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" {  } { { "adder.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adder.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder Vtab:inst1\|addbcd:ad1\|adder:A1 " "Info: Elaborating entity \"adder\" for hierarchy \"Vtab:inst1\|addbcd:ad1\|adder:A1\"" {  } { { "addbcd.vhd" "A1" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/addbcd.vhd" 29 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "bcdadder.vhd 2 1 " "Warning: Using design file bcdadder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcdadder-Na " "Info: Found design unit 1: bcdadder-Na" {  } { { "bcdadder.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/bcdadder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 bcdadder " "Info: Found entity 1: bcdadder" {  } { { "bcdadder.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/bcdadder.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcdadder Vtab:inst1\|addbcd:ad1\|adder:A1\|bcdadder:U1 " "Info: Elaborating entity \"bcdadder\" for hierarchy \"Vtab:inst1\|addbcd:ad1\|adder:A1\|bcdadder:U1\"" {  } { { "adder.vhd" "U1" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/adder.vhd" 24 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "re bcdadder.vhd(21) " "Warning (10492): VHDL Process Statement warning at bcdadder.vhd(21): signal \"re\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "bcdadder.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/bcdadder.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "re bcdadder.vhd(22) " "Warning (10492): VHDL Process Statement warning at bcdadder.vhd(22): signal \"re\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "bcdadder.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/bcdadder.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "sinA.vhd 2 1 " "Warning: Using design file sinA.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sinA-b " "Info: Found design unit 1: sinA-b" {  } { { "sinA.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/sinA.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sinA " "Info: Found entity 1: sinA" {  } { { "sinA.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/sinA.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sinA sinA:inst7 " "Info: Elaborating entity \"sinA\" for hierarchy \"sinA:inst7\"" {  } { { "ad0820.bdf" "inst7" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { -120 408 576 -24 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "findmax findmax:inst10 " "Info: Elaborating entity \"findmax\" for hierarchy \"findmax:inst10\"" {  } { { "ad0820.bdf" "inst10" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { -120 176 344 -24 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_fre d_fre:inst8 " "Info: Elaborating entity \"d_fre\" for hierarchy \"d_fre:inst8\"" {  } { { "ad0820.bdf" "inst8" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { 192 0 96 288 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frequence frequence:inst9 " "Info: Elaborating entity \"frequence\" for hierarchy \"frequence:inst9\"" {  } { { "ad0820.bdf" "inst9" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { 192 408 552 320 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onehz_clk onehz_clk:inst6 " "Info: Elaborating entity \"onehz_clk\" for hierarchy \"onehz_clk:inst6\"" {  } { { "ad0820.bdf" "inst6" { Schematic "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/ad0820.bdf" { { 232 152 248 328 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sinA:inst7\|da1_8\[5\] data_in GND " "Warning (14130): Reduced register \"sinA:inst7\|da1_8\[5\]\" with stuck data_in port to stuck value GND" {  } { { "sinA.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/sinA.vhd" 94 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sinA:inst7\|da1_8\[6\] data_in GND " "Warning (14130): Reduced register \"sinA:inst7\|da1_8\[6\]\" with stuck data_in port to stuck value GND" {  } { { "sinA.vhd" "" { Text "C:/Documents and Settings/IBM-WSQ/桌面/北邮/5.33/ad0820/sinA.vhd" 94 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}